From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 24 Sep 2014 02:17:09 +0000 (+0000)
Subject: R600/SI: Fix hardcoded and wrong operand numbers.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=2e67962e9bf4dbfe73bfe3f2088774af8ac5aad3;hp=9b50273e54a2a6afb3c663b585af24d8da6c4574;p=oota-llvm.git

R600/SI: Fix hardcoded and wrong operand numbers.

Also fix leftover debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218359 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index e53db58123b..41e6d37e014 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -1069,11 +1069,9 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
   // Verify misc. restrictions on specific instructions.
   if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
       Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
-    MI->dump();
-
-    const MachineOperand &Src0 = MI->getOperand(2);
-    const MachineOperand &Src1 = MI->getOperand(3);
-    const MachineOperand &Src2 = MI->getOperand(4);
+    const MachineOperand &Src0 = MI->getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI->getOperand(Src1Idx);
+    const MachineOperand &Src2 = MI->getOperand(Src2Idx);
     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
       if (!compareMachineOp(Src0, Src1) &&
           !compareMachineOp(Src0, Src2)) {