From: Chris Lattner Date: Fri, 3 Feb 2006 18:54:24 +0000 (+0000) Subject: Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=299f9bab47d53ca79be5c9ed53f22fd5846b9cd6;hp=d77525da5e120eeaccf2322340111b1d65c49211;p=oota-llvm.git Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now obsolete. yaay :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25939 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index c29fef2e607..6d645f19b41 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -38,11 +38,6 @@ FunctionPass *createX86ISelPattern(TargetMachine &TM); /// FunctionPass *createX86ISelDag(TargetMachine &TM); -/// createX86PeepholeOptimizer - Create a pass to perform X86 specific peephole -/// optimizations. -/// -FunctionPass *createX86PeepholeOptimizerPass(); - /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into /// floating point stack references and physical instructions. diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp deleted file mode 100644 index 40735459d6a..00000000000 --- a/lib/Target/X86/X86PeepholeOpt.cpp +++ /dev/null @@ -1,178 +0,0 @@ -//===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains an immediate shrinker for the X86. FIXME: Remove when -// the dag isel makes this obsolete! -// -//===----------------------------------------------------------------------===// - -#include "X86.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/Target/MRegisterInfo.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/ADT/STLExtras.h" -using namespace llvm; - -namespace { - Statistic<> NumPHOpts("x86-peephole", - "Number of peephole optimization performed"); - Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded"); - struct PH : public MachineFunctionPass { - virtual bool runOnMachineFunction(MachineFunction &MF); - - bool PeepholeOptimize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I); - - virtual const char *getPassName() const { return "X86 Peephole Optimizer"; } - }; -} - -FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); } - -bool PH::runOnMachineFunction(MachineFunction &MF) { - bool Changed = false; - - for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI) - for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ) - if (PeepholeOptimize(*BI, I)) { - Changed = true; - ++NumPHOpts; - } else - ++I; - - return Changed; -} - - -bool PH::PeepholeOptimize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I) { - assert(I != MBB.end()); - MachineBasicBlock::iterator NextI = next(I); - - MachineInstr *MI = I; - MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0; - unsigned Size = 0; - switch (MI->getOpcode()) { - // A large number of X86 instructions have forms which take an 8-bit - // immediate despite the fact that the operands are 16 or 32 bits. Because - // this can save three bytes of code size (and icache space), we want to - // shrink them if possible. - case X86::IMUL16rri: case X86::IMUL32rri: - assert(MI->getNumOperands() == 3 && "These should all have 3 operands!"); - if (MI->getOperand(2).isImmediate()) { - int Val = MI->getOperand(2).getImmedValue(); - // If the value is the same when signed extended from 8 bits... - if (Val == (signed int)(signed char)Val) { - unsigned Opcode; - switch (MI->getOpcode()) { - default: assert(0 && "Unknown opcode value!"); - case X86::IMUL16rri: Opcode = X86::IMUL16rri8; break; - case X86::IMUL32rri: Opcode = X86::IMUL32rri8; break; - } - unsigned R0 = MI->getOperand(0).getReg(); - unsigned R1 = MI->getOperand(1).getReg(); - I = MBB.insert(MBB.erase(I), - BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val)); - return true; - } - } - return false; - - case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri: - case X86::SUB16ri: case X86::SUB32ri: - case X86::SBB16ri: case X86::SBB32ri: - case X86::AND16ri: case X86::AND32ri: - case X86::OR16ri: case X86::OR32ri: - case X86::XOR16ri: case X86::XOR32ri: - assert(MI->getNumOperands() == 2 && "These should all have 2 operands!"); - if (MI->getOperand(1).isImmediate()) { - int Val = MI->getOperand(1).getImmedValue(); - // If the value is the same when signed extended from 8 bits... - if (Val == (signed int)(signed char)Val) { - unsigned Opcode; - switch (MI->getOpcode()) { - default: assert(0 && "Unknown opcode value!"); - case X86::ADD16ri: Opcode = X86::ADD16ri8; break; - case X86::ADD32ri: Opcode = X86::ADD32ri8; break; - case X86::ADC32ri: Opcode = X86::ADC32ri8; break; - case X86::SUB16ri: Opcode = X86::SUB16ri8; break; - case X86::SUB32ri: Opcode = X86::SUB32ri8; break; - case X86::SBB16ri: Opcode = X86::SBB16ri8; break; - case X86::SBB32ri: Opcode = X86::SBB32ri8; break; - case X86::AND16ri: Opcode = X86::AND16ri8; break; - case X86::AND32ri: Opcode = X86::AND32ri8; break; - case X86::OR16ri: Opcode = X86::OR16ri8; break; - case X86::OR32ri: Opcode = X86::OR32ri8; break; - case X86::XOR16ri: Opcode = X86::XOR16ri8; break; - case X86::XOR32ri: Opcode = X86::XOR32ri8; break; - } - unsigned R0 = MI->getOperand(0).getReg(); - I = MBB.insert(MBB.erase(I), - BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef) - .addZImm((char)Val)); - return true; - } - } - return false; - - case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi: - case X86::SUB16mi: case X86::SUB32mi: - case X86::SBB16mi: case X86::SBB32mi: - case X86::AND16mi: case X86::AND32mi: - case X86::OR16mi: case X86::OR32mi: - case X86::XOR16mi: case X86::XOR32mi: - assert(MI->getNumOperands() == 5 && "These should all have 5 operands!"); - if (MI->getOperand(4).isImmediate()) { - int Val = MI->getOperand(4).getImmedValue(); - // If the value is the same when signed extended from 8 bits... - if (Val == (signed int)(signed char)Val) { - unsigned Opcode; - switch (MI->getOpcode()) { - default: assert(0 && "Unknown opcode value!"); - case X86::ADD16mi: Opcode = X86::ADD16mi8; break; - case X86::ADD32mi: Opcode = X86::ADD32mi8; break; - case X86::ADC32mi: Opcode = X86::ADC32mi8; break; - case X86::SUB16mi: Opcode = X86::SUB16mi8; break; - case X86::SUB32mi: Opcode = X86::SUB32mi8; break; - case X86::SBB16mi: Opcode = X86::SBB16mi8; break; - case X86::SBB32mi: Opcode = X86::SBB32mi8; break; - case X86::AND16mi: Opcode = X86::AND16mi8; break; - case X86::AND32mi: Opcode = X86::AND32mi8; break; - case X86::OR16mi: Opcode = X86::OR16mi8; break; - case X86::OR32mi: Opcode = X86::OR32mi8; break; - case X86::XOR16mi: Opcode = X86::XOR16mi8; break; - case X86::XOR32mi: Opcode = X86::XOR32mi8; break; - } - unsigned R0 = MI->getOperand(0).getReg(); - unsigned Scale = MI->getOperand(1).getImmedValue(); - unsigned R1 = MI->getOperand(2).getReg(); - if (MI->getOperand(3).isImmediate()) { - unsigned Offset = MI->getOperand(3).getImmedValue(); - I = MBB.insert(MBB.erase(I), - BuildMI(Opcode, 5).addReg(R0).addZImm(Scale). - addReg(R1).addSImm(Offset).addZImm((char)Val)); - } else if (MI->getOperand(3).isGlobalAddress()) { - GlobalValue *GA = MI->getOperand(3).getGlobal(); - int Offset = MI->getOperand(3).getOffset(); - I = MBB.insert(MBB.erase(I), - BuildMI(Opcode, 5).addReg(R0).addZImm(Scale). - addReg(R1).addGlobalAddress(GA, false, Offset). - addZImm((char)Val)); - } - return true; - } - } - return false; - default: - return false; - } -} diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 6207a274775..970cbd450e9 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -129,8 +129,6 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out, // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); - PM.add(createX86PeepholeOptimizerPass()); - if (PrintMachineCode) // Print the register-allocated code PM.add(createX86CodePrinterPass(std::cerr, *this)); @@ -198,8 +196,6 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); - PM.add(createX86PeepholeOptimizerPass()); - if (PrintMachineCode) // Print the register-allocated code PM.add(createX86CodePrinterPass(std::cerr, TM)); }