From: Zoran Jovanovic Date: Fri, 27 Feb 2015 15:03:50 +0000 (+0000) Subject: [mips][microMIPS] Change register class for GP register X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=2846ef368045c7ca39d4e92198d3e46b697541f6;p=oota-llvm.git [mips][microMIPS] Change register class for GP register Differential Revision: http://reviews.llvm.org/D7934 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230760 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsMachineFunction.cpp b/lib/Target/Mips/MipsMachineFunction.cpp index 30b93dcb275..09e722d331f 100644 --- a/lib/Target/Mips/MipsMachineFunction.cpp +++ b/lib/Target/Mips/MipsMachineFunction.cpp @@ -79,14 +79,19 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() { if (GlobalBaseReg) return GlobalBaseReg; + MipsSubtarget const &STI = + static_cast(MF.getSubtarget()); + const TargetRegisterClass *RC = - static_cast(MF.getSubtarget()).inMips16Mode() + STI.inMips16Mode() ? &Mips::CPU16RegsRegClass - : static_cast(MF.getTarget()) - .getABI() - .IsN64() - ? &Mips::GPR64RegClass - : &Mips::GPR32RegClass; + : STI.inMicroMipsMode() + ? &Mips::GPRMM16RegClass + : static_cast(MF.getTarget()) + .getABI() + .IsN64() + ? &Mips::GPR64RegClass + : &Mips::GPR32RegClass; return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); } diff --git a/test/CodeGen/Mips/micromips-gp-rc.ll b/test/CodeGen/Mips/micromips-gp-rc.ll new file mode 100644 index 00000000000..945917a3c89 --- /dev/null +++ b/test/CodeGen/Mips/micromips-gp-rc.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@g = external global i32 + +; Function Attrs: noreturn nounwind +define void @foo() #0 { +entry: + %0 = load i32* @g, align 4 + tail call void @exit(i32 signext %0) + unreachable +} + +; Function Attrs: noreturn +declare void @exit(i32 signext) + +; CHECK: move $gp, ${{[0-9]+}} +