From: Evan Cheng <evan.cheng@apple.com>
Date: Mon, 19 Jan 2009 19:06:11 +0000 (+0000)
Subject: DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=2722e7b1394e675114d2338ce61a92814d66d126;p=oota-llvm.git

DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 842bb13ae82..9b42d00b654 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1405,7 +1405,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
         InFlag =
           CurDAG->getCopyToReg(CurDAG->getEntryNode(),
                                LoReg, N0, SDValue()).getValue(1);
-        if (isSigned) {
+        if (isSigned && !CurDAG->SignBitIsZero(N0)) {
           // Sign extend the low part into the high part.
           InFlag =
             SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
diff --git a/test/CodeGen/X86/rem-2.ll b/test/CodeGen/X86/rem-2.ll
new file mode 100644
index 00000000000..3e17fc0b430
--- /dev/null
+++ b/test/CodeGen/X86/rem-2.ll
@@ -0,0 +1,7 @@
+; RUN: llvm-as < %s | llc -march=x86 | not grep cltd
+
+define i32 @test(i32 %X) nounwind readnone {
+entry:
+	%0 = srem i32 41, %X
+	ret i32 %0
+}