From: Jakob Stoklund Olesen Date: Sun, 2 Aug 2009 18:27:36 +0000 (+0000) Subject: Add support for CPU features (i.e., bugs) and workarounds. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=26a84d4f3c9f7bf88678dd7574261ec66c4f8952;p=oota-llvm.git Add support for CPU features (i.e., bugs) and workarounds. This is just the framework to identify the needed workarounds. They are not actually implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77902 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Blackfin/Blackfin.td b/lib/Target/Blackfin/Blackfin.td index 0b73d1f4db9..b9046383fa6 100644 --- a/lib/Target/Blackfin/Blackfin.td +++ b/lib/Target/Blackfin/Blackfin.td @@ -20,8 +20,53 @@ include "llvm/Target/Target.td" // Blackfin Subtarget features. //===----------------------------------------------------------------------===// -def FeatureSSYNC : SubtargetFeature<"ssync","ssyncWorkaround", "true", - "Work around SSYNC bugs">; +def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true", + "Build for SDRAM">; + +def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true", + "Assume instruction cache lookaside buffers are enabled at runtime">; + +//===----------------------------------------------------------------------===// +// Bugs in the silicon becomes workarounds in the compiler. +// See http://www.analog.com/ for the full list of IC anomalies. +//===----------------------------------------------------------------------===// + +def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true", + "Work around 05000074 - " + "Multi-Issue Instruction with dsp32shiftimm and P-reg Store">; + +def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true", + "Work around 05000244 - " + "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">; + +def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true", + "Work around 05000245 - " + "Access in the Shadow of a Conditional Branch">; + +def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true", + "Work around 05000257 - " + "Interrupt/Exception During Short Hardware Loop">; + +def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true", + "Work around 05000283 - " + "System MMR Write Is Stalled Indefinitely when Killed">; + +def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true", + "Work around 05000312 - " + "SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">; + +def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly", + "wa_killed_mmr", "true", + "Work around 05000315 - " + "Killed System MMR Write Completes Erroneously on Next System MMR Access">; + +def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true", + "Work around 05000371 - " + "Possible RETS Register Corruption when Subroutine Is under 5 Cycles">; + +def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true", + "Work around 05000426 - " + "Speculative Fetches of Indirect-Pointer Instructions">; //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions @@ -37,10 +82,114 @@ def BlackfinInstrInfo : InstrInfo {} // Blackfin processors supported. //===----------------------------------------------------------------------===// -class Proc Features> - : Processor; +class Proc Features> + : Processor; + +def : Proc<"generic", "", []>; + +multiclass Core Features> { + def : Proc; + def : Proc; + def : Proc; +} + +multiclass CoreEdinburgh + : Core { + def : Proc; + def : Proc; + def : Proc; + def : Proc; +} +multiclass CoreBraemar + : Core { + def : Proc; + def : Proc; +} +multiclass CoreStirling + : Core { + def : Proc; + def : Proc; + def : Proc; +} +multiclass CoreMoab + : Core { + def : Proc; + def : Proc; + def : Proc; + def : Proc; +} +multiclass CoreTeton + : Core { + def : Proc; + def : Proc; +} +multiclass CoreKookaburra + : Core { + def : Proc; + def : Proc; + def : Proc; +} +multiclass CoreMockingbird + : Core { + def : Proc; + def : Proc; +} +multiclass CoreBrodie + : Core { + def : Proc; + def : Proc; +} -def : Proc<"generic", [FeatureSSYNC]>; +defm BF512 : CoreBrodie<"bf512">; +defm BF514 : CoreBrodie<"bf514">; +defm BF516 : CoreBrodie<"bf516">; +defm BF518 : CoreBrodie<"bf518">; +defm BF522 : CoreMockingbird<"bf522">; +defm BF523 : CoreKookaburra<"bf523">; +defm BF524 : CoreMockingbird<"bf524">; +defm BF525 : CoreKookaburra<"bf525">; +defm BF526 : CoreMockingbird<"bf526">; +defm BF527 : CoreKookaburra<"bf527">; +defm BF531 : CoreEdinburgh<"bf531">; +defm BF532 : CoreEdinburgh<"bf532">; +defm BF533 : CoreEdinburgh<"bf533">; +defm BF534 : CoreBraemar<"bf534">; +defm BF536 : CoreBraemar<"bf536">; +defm BF537 : CoreBraemar<"bf537">; +defm BF538 : CoreStirling<"bf538">; +defm BF539 : CoreStirling<"bf539">; +defm BF542 : CoreMoab<"bf542">; +defm BF544 : CoreMoab<"bf544">; +defm BF548 : CoreMoab<"bf548">; +defm BF549 : CoreMoab<"bf549">; +defm BF561 : CoreTeton<"bf561">; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/lib/Target/Blackfin/BlackfinSubtarget.cpp b/lib/Target/Blackfin/BlackfinSubtarget.cpp index cf14b105aaf..80a242182d8 100644 --- a/lib/Target/Blackfin/BlackfinSubtarget.cpp +++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp @@ -18,9 +18,20 @@ using namespace llvm; BlackfinSubtarget::BlackfinSubtarget(const TargetMachine &TM, const Module &M, - const std::string &FS) { + const std::string &FS) + : sdram(false), + icplb(false), + wa_mi_shift(false), + wa_csync(false), + wa_specld(false), + wa_mmr_stall(false), + wa_lcregs(false), + wa_hwloop(false), + wa_ind_call(false), + wa_killed_mmr(false), + wa_rets(false) +{ std::string CPU = "generic"; - // Parse features string. ParseSubtargetFeatures(FS, CPU); } diff --git a/lib/Target/Blackfin/BlackfinSubtarget.h b/lib/Target/Blackfin/BlackfinSubtarget.h index 31df9c0fee9..13d8e240ab6 100644 --- a/lib/Target/Blackfin/BlackfinSubtarget.h +++ b/lib/Target/Blackfin/BlackfinSubtarget.h @@ -23,7 +23,17 @@ namespace llvm { class Module; class BlackfinSubtarget : public TargetSubtarget { - bool ssyncWorkaround; + bool sdram; + bool icplb; + bool wa_mi_shift; + bool wa_csync; + bool wa_specld; + bool wa_mmr_stall; + bool wa_lcregs; + bool wa_hwloop; + bool wa_ind_call; + bool wa_killed_mmr; + bool wa_rets; public: BlackfinSubtarget(const TargetMachine &TM, const Module &M, const std::string &FS); diff --git a/lib/Target/Blackfin/README.txt b/lib/Target/Blackfin/README.txt index 67c1e514bc7..b4c8227cd64 100644 --- a/lib/Target/Blackfin/README.txt +++ b/lib/Target/Blackfin/README.txt @@ -170,3 +170,75 @@ Stores: | I-- | * | | * | * | | | I++M | * | | | | | +* Workarounds and features +Blackfin CPUs have bugs. Each model comes in a number of silicon revisions with +different bugs. We learn about the CPU model from the -mcpu switch. + +** Interpretation of -mcpu value +- -mcpu=bf527 refers to the latest known BF527 revision +- -mcpu=bf527-0.2 refers to silicon rev. 0.2 +- -mcpu=bf527-any refers to all known revisions +- -mcpu=bf527-none disables all workarounds + +The -mcpu setting affects the __SILICON_REVISION__ macro and enabled workarounds: + +| -mcpu | __SILICON_REVISION__ | Workarounds | +|------------+----------------------+--------------------| +| bf527 | Def Latest | Specific to latest | +| bf527-1.3 | Def 0x0103 | Specific to 1.3 | +| bf527-any | Def 0xffff | All bf527-x.y | +| bf527-none | Undefined | None | + +These are the known cores and revisions: + +| Core | Silicon | Processors | +|-------------+--------------------+-------------------------| +| Edinburgh | 0.3, 0.4, 0.5, 0.6 | BF531 BF532 BF533 | +| Braemar | 0.2, 0.3 | BF534 BF536 BF537 | +| Stirling | 0.3, 0.4, 0.5 | BF538 BF539 | +| Moab | 0.0, 0.1, 0.2 | BF542 BF544 BF548 BF549 | +| Teton | 0.3, 0.5 | BF561 | +| Kookaburra | 0.0, 0.1, 0.2 | BF523 BF525 BF527 | +| Mockingbird | 0.0, 0.1 | BF522 BF524 BF526 | +| Brodie | 0.0, 0.1 | BF512 BF514 BF516 BF518 | + + +** Compiler implemented workarounds +Most workarounds are implemented in header files and source code using the +__ADSPBF527__ macros. A few workarounds require compiler support. + +| Anomaly | Macro | GCC Switch | +|----------+--------------------------------+------------------| +| Any | __WORKAROUNDS_ENABLED | | +| 05000074 | WA_05000074 | | +| 05000244 | __WORKAROUND_SPECULATIVE_SYNCS | -mcsync-anomaly | +| 05000245 | __WORKAROUND_SPECULATIVE_LOADS | -mspecld-anomaly | +| 05000257 | WA_05000257 | | +| 05000283 | WA_05000283 | | +| 05000312 | WA_LOAD_LCREGS | | +| 05000315 | WA_05000315 | | +| 05000371 | __WORKAROUND_RETS | | +| 05000426 | __WORKAROUND_INDIRECT_CALLS | Not -micplb | + +** GCC feature switches +| Switch | Description | +|---------------------------+----------------------------------------| +| -msim | Use simulator runtime | +| -momit-leaf-frame-pointer | Omit frame pointer for leaf functions | +| -mlow64k | | +| -mcsync-anomaly | | +| -mspecld-anomaly | | +| -mid-shared-library | | +| -mleaf-id-shared-library | | +| -mshared-library-id= | | +| -msep-data | Enable separate data segment | +| -mlong-calls | Use indirect calls | +| -mfast-fp | | +| -mfdpic | | +| -minline-plt | | +| -mstack-check-l1 | Do stack checking in L1 scratch memory | +| -mmulticore | Enable multicore support | +| -mcorea | Build for Core A | +| -mcoreb | Build for Core B | +| -msdram | Build for SDRAM | +| -micplb | Assume ICPLBs are enabled at runtime. |