From: Hal Finkel <hfinkel@anl.gov>
Date: Wed, 27 Mar 2013 13:00:56 +0000 (+0000)
Subject: Fix target-customized spilling in the register scavenger
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=26998ee794e9b6f9b0bc27d1e273b6b78afce57d;p=oota-llvm.git

Fix target-customized spilling in the register scavenger

This is a follow-up to r178073 (which should actually make target-customized
spilling work again).

I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).

Patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 6b85cd93cf3..55a66ba5482 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -371,7 +371,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
     if (Scavenged[SI].Reg == 0)
       break;
 
-  if (SI < Scavenged.size()) {
+  if (SI == Scavenged.size()) {
     // We need to scavenge a register but have no spill slot, the target
     // must know how to do it (if not, we'll assert below).
     Scavenged.push_back(ScavengedInfo());