From: Chris Lattner <sabre@nondot.org>
Date: Tue, 5 Oct 2010 23:00:14 +0000 (+0000)
Subject: Use #NAME# to have the CMOV multiclass define things with the same names as before
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=25cbf504fe803a0b57e877c6f83aed5aa48e7ec7;p=oota-llvm.git

Use #NAME# to have the CMOV multiclass define things with the same names as before
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 048c7bb932d..018ea9e8f6a 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1538,9 +1538,9 @@ static bool HasNoSignedComparisonUses(SDNode *N) {
       case X86::CMOVB16rr: case X86::CMOVB16rm:
       case X86::CMOVB32rr: case X86::CMOVB32rm:
       case X86::CMOVB64rr: case X86::CMOVB64rm:
-      case X86::CMOVBErr16: case X86::CMOVBErm16:
-      case X86::CMOVBErr32: case X86::CMOVBErm32:
-      case X86::CMOVBErr64: case X86::CMOVBErm64:
+      case X86::CMOVBE16rr: case X86::CMOVBE16rm:
+      case X86::CMOVBE32rr: case X86::CMOVBE32rm:
+      case X86::CMOVBE64rr: case X86::CMOVBE64rm:
       case X86::CMOVE16rr: case X86::CMOVE16rm:
       case X86::CMOVE32rr: case X86::CMOVE32rm:
       case X86::CMOVE64rr: case X86::CMOVE64rm:
diff --git a/lib/Target/X86/X86InstrCMovSetCC.td b/lib/Target/X86/X86InstrCMovSetCC.td
index c0df8ac6fb7..f22fe4de768 100644
--- a/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/lib/Target/X86/X86InstrCMovSetCC.td
@@ -17,36 +17,39 @@
 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
   let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
       isCommutable = 1 in {
-    def rr16 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
-                 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
-                 [(set GR16:$dst,
-                       (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,
-               TB, OpSize;
-    def rr32 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
-                 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
-                 [(set GR32:$dst,
-                       (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>,
-               TB;
-    def rr64 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
-                 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
-                 [(set GR64:$dst,
-                       (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>,
-              TB;
+    def #NAME#16rr
+      : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+          !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR16:$dst,
+                (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
+    def #NAME#32rr
+      : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+          !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR32:$dst,
+                (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
+    def #NAME#64rr
+      :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+          !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR64:$dst,
+                (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
   }
 
   let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"in {
-  def rm16 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
-               !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
-               [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
-                                         CondNode, EFLAGS))]>, TB, OpSize;
-  def rm32 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
-               !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
-               [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
-                                         CondNode, EFLAGS))]>, TB;
-  def rm64 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
-               !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
-               [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
-                                         CondNode, EFLAGS))]>, TB;
+    def #NAME#16rm
+      : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+          !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+                                    CondNode, EFLAGS))]>, TB, OpSize;
+    def #NAME#32rm
+      : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+          !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+                                    CondNode, EFLAGS))]>, TB;
+    def #NAME#64rm
+      :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
+          !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
+          [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                    CondNode, EFLAGS))]>, TB;
   } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
 } // end multiclass
 
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 4dc412b05e1..39901764052 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -865,7 +865,7 @@ defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
-defm : CMOVmr<X86_COND_A , CMOVBErm16, CMOVBErm32, CMOVBErm64>;
+defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 14382d7a674..dd4940b4ed2 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -482,9 +482,9 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
     { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
     { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
     { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
-    { X86::CMOVBErr16,      X86::CMOVBErm16, 0 },
-    { X86::CMOVBErr32,      X86::CMOVBErm32, 0 },
-    { X86::CMOVBErr64,      X86::CMOVBErm64, 0 },
+    { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
+    { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
+    { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
     { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
     { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
     { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
@@ -1445,9 +1445,9 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
   case X86::CMOVNE16rr:
   case X86::CMOVNE32rr:
   case X86::CMOVNE64rr:
-  case X86::CMOVBErr16:
-  case X86::CMOVBErr32:
-  case X86::CMOVBErr64:
+  case X86::CMOVBE16rr:
+  case X86::CMOVBE32rr:
+  case X86::CMOVBE64rr:
   case X86::CMOVA16rr:
   case X86::CMOVA32rr:
   case X86::CMOVA64rr:
@@ -1496,12 +1496,12 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
-    case X86::CMOVBErr16: Opc = X86::CMOVA16rr; break;
-    case X86::CMOVBErr32: Opc = X86::CMOVA32rr; break;
-    case X86::CMOVBErr64: Opc = X86::CMOVA64rr; break;
-    case X86::CMOVA16rr:  Opc = X86::CMOVBErr16; break;
-    case X86::CMOVA32rr:  Opc = X86::CMOVBErr32; break;
-    case X86::CMOVA64rr:  Opc = X86::CMOVBErr64; break;
+    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
+    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
+    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
+    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
+    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
+    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;