From: Kevin Enderby <enderby@apple.com>
Date: Tue, 24 Apr 2012 17:45:56 +0000 (+0000)
Subject: Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=24e767d076cb17838c2c13cabe9d275bea34a6d8;p=oota-llvm.git

Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index e7bc808ac94..5f2130b2bf5 100644
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -1734,6 +1734,25 @@
 0xcf 0x1a 0xe0 0xf4
 # CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
 
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]
+0x0f 0x0e 0xa4 0xf4
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]!
+0x0d 0x0e 0xa4 0xf4
+# CHECK: vld3.8	{d0[], d2[], d4[]}, [r4], r5
+0x25 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4]
+0x6f 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d1[], d2[]}, [r4]!
+0x4d 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4], r5
+0x65 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]
+0x8f 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]!
+0x8d 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d2[], d4[]}, [r4], r5
+0xa5 0x0e 0xa4 0xf4
+
 0x3f 0x03 0xe0 0xf4
 # CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
 0x4f 0x07 0xe0 0xf4
diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index 3816fd7ec46..9c4233b4b5d 100644
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1475,6 +1475,25 @@
 0xe0 0xf9 0xcf 0x1a
 # CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
 
+0xa4 0xf9 0x0f 0x0e
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]
+0xa4 0xf9 0x0d 0x0e
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0x25 0x0e
+# CHECK: vld3.8	{d0[], d2[], d4[]}, [r4], r5
+0xa4 0xf9 0x6f 0x0e
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4]
+0xa4 0xf9 0x4d 0x0e
+# CHECK: vld3.16	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0x65 0x0e
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4], r5
+0xa4 0xf9 0x8f 0x0e
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]
+0xa4 0xf9 0x8d 0x0e
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0xa5 0x0e
+# CHECK: vld3.32	{d0[], d2[], d4[]}, [r4], r5
+
 0xe0 0xf9 0x3f 0x03
 # CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
 0xe0 0xf9 0x4f 0x07