From: Bob Wilson Date: Tue, 29 Jun 2010 20:13:29 +0000 (+0000) Subject: Add support for encoding VDUP (ARM core register) instructions. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=21773e716f72babacfcf98cb5a90fc1a62a8254d;p=oota-llvm.git Add support for encoding VDUP (ARM core register) instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 2c8939fdf0f..7895cb07192 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -141,6 +141,7 @@ namespace { void emitMiscInstruction(const MachineInstr &MI); void emitNEONLaneInstruction(const MachineInstr &MI); + void emitNEONDupInstruction(const MachineInstr &MI); void emitNEON1RegModImmInstruction(const MachineInstr &MI); void emitNEON2RegInstruction(const MachineInstr &MI); void emitNEON3RegInstruction(const MachineInstr &MI); @@ -420,6 +421,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { case ARMII::NSetLnFrm: emitNEONLaneInstruction(MI); break; + case ARMII::NDupFrm: + emitNEONDupInstruction(MI); + break; case ARMII::N1RegModImmFrm: emitNEON1RegModImmInstruction(MI); break; @@ -1638,6 +1642,19 @@ void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { emitWordLE(Binary); } +void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; + + unsigned RegT = MI.getOperand(1).getReg(); + RegT = ARMRegisterInfo::getRegisterNumbering(RegT); + Binary |= (RegT << ARMII::RegRdShift); + Binary |= encodeNEONRn(MI, 0); + emitWordLE(Binary); +} + void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { unsigned Binary = getBinaryCodeForInstr(MI); // Destination register is encoded in Dd.