From: Jacob Chen <jacob2.chen@rock-chips.com>
Date: Wed, 7 Dec 2016 08:37:42 +0000 (+0800)
Subject: FROMLIST: phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup
X-Git-Tag: firefly_0821_release~1131
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=2067c051d185334859db62b9d422042cc88023a3;p=firefly-linux-kernel-4.4.55.git

FROMLIST: phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Change-Id: Iad8f52b623df3c4460dc321bb55e9c3111455590
Signed-off-by: Randy Li <ayaka@soulik.info>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
 (am from https://patchwork.kernel.org/patch/9324163/)
---

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index 597dea0cca41..98334f0c8a9e 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -28,6 +28,9 @@ Optional Properties:
 - clock-names: string, clock name, must be "phyclk"
 - vbus_drv-gpio: pull gpio on/off to control vbus power supply.
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+- phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
@@ -36,6 +39,8 @@ usbphy: phy {
 	rockchip,grf = <&grf>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	resets = <&cru SRST_USBHOST1_PHY>;
+	reset-names = "phy-reset";
 
 	usbphy0: usb-phy0 {
 		#phy-cells = <0>;
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 39f419d6d484..898683414f47 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -30,6 +30,7 @@
 #include <linux/reset.h>
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
+#include <linux/delay.h>
 
 /*
  * The higher 16-bit of this register is used for write protection
@@ -74,6 +75,7 @@ struct rockchip_usb_phy {
 	struct clk      *clk480m;
 	struct clk_hw	clk480m_hw;
 	struct phy	*phy;
+	struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -172,9 +174,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
 	return ret;
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+	if (phy->reset) {
+		reset_control_assert(phy->reset);
+		udelay(10);
+		reset_control_deassert(phy->reset);
+	}
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on	= rockchip_usb_phy_power_on,
 	.power_off	= rockchip_usb_phy_power_off,
+	.reset		= rockchip_usb_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
@@ -211,6 +227,10 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 		return -EINVAL;
 	}
 
+	rk_phy->reset = of_reset_control_get(child, "phy-reset");
+	if (IS_ERR(rk_phy->reset))
+		rk_phy->reset = NULL;
+
 	rk_phy->reg_offset = reg_offset;
 
 	rk_phy->clk = of_clk_get_by_name(child, "phyclk");