From: zsq Date: Tue, 17 Mar 2015 06:38:08 +0000 (+0800) Subject: rga2 support 32bit compile at 64bit platform X-Git-Tag: firefly_0821_release~4158^2~349 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=1e79010fe3ceb635022fe12ec175bc135f134607;p=firefly-linux-kernel-4.4.55.git rga2 support 32bit compile at 64bit platform --- diff --git a/drivers/video/rockchip/rga2/rga2.h b/drivers/video/rockchip/rga2/rga2.h old mode 100644 new mode 100755 index 545454e187f6..467ef13683dd --- a/drivers/video/rockchip/rga2/rga2.h +++ b/drivers/video/rockchip/rga2/rga2.h @@ -223,6 +223,12 @@ typedef struct MMU uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ } MMU; +typedef struct MMU_32 +{ + unsigned char mmu_en; + uint32_t base_addr; + uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ +} MMU_32; typedef struct RECT { @@ -268,6 +274,22 @@ typedef struct rga_img_info_t unsigned short alpha_swap; } rga_img_info_t; +typedef struct rga_img_info_32_t +{ + uint32_t yrgb_addr; /* yrgb mem addr */ + uint32_t uv_addr; /* cb/cr mem addr */ + uint32_t v_addr; /* cr mem addr */ + unsigned int format; //definition by RK_FORMAT + unsigned short act_w; + unsigned short act_h; + unsigned short x_offset; + unsigned short y_offset; + unsigned short vir_w; + unsigned short vir_h; + unsigned short endian_mode; //for BPP + unsigned short alpha_swap; +} +rga_img_info_32_t; struct rga_req { uint8_t render_mode; /* (enum) process mode sel */ @@ -341,6 +363,56 @@ struct rga_req { uint8_t src_trans_mode; }; +struct rga_req_32 +{ + uint8_t render_mode; /* (enum) process mode sel */ + rga_img_info_32_t src; /* src image info */ + rga_img_info_32_t dst; /* dst image info */ + rga_img_info_32_t pat; /* patten image info */ + uint32_t rop_mask_addr; /* rop4 mask addr */ + uint32_t LUT_addr; /* LUT addr */ + RECT clip; /* dst clip window default value is dst_vir */ + /* value from [0, w-1] / [0, h-1]*/ + int32_t sina; /* dst angle default value 0 16.16 scan from table */ + int32_t cosa; /* dst angle default value 0 16.16 scan from table */ + uint16_t alpha_rop_flag; /* alpha rop process flag */ + /* ([0] = 1 alpha_rop_enable) */ + /* ([1] = 1 rop enable) */ + /* ([2] = 1 fading_enable) */ + /* ([3] = 1 PD_enable) */ + /* ([4] = 1 alpha cal_mode_sel) */ + /* ([5] = 1 dither_enable) */ + /* ([6] = 1 gradient fill mode sel) */ + /* ([7] = 1 AA_enable) */ + uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ + uint32_t color_key_max; /* color key max */ + uint32_t color_key_min; /* color key min */ + uint32_t fg_color; /* foreground color */ + uint32_t bg_color; /* background color */ + COLOR_FILL gr_color; /* color fill use gradient */ + line_draw_t line_draw_info; + FADING fading; + uint8_t PD_mode; /* porter duff alpha mode sel */ + uint8_t alpha_global_value; /* global alpha value */ + uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ + uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ + uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ + uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ + uint8_t endian_mode; /* 0/big endian 1/little endian*/ + uint8_t rotate_mode; /* (enum) rotate mode */ + /* 0x0, no rotate */ + /* 0x1, rotate */ + /* 0x2, x_mirror */ + /* 0x3, y_mirror */ + uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ + MMU_32 mmu_info; /* mmu information */ + uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ + /* ([2~3] rop mode) */ + /* ([4] zero mode en) */ + /* ([5] dst alpha mode) */ + /* ([6] alpha output mode sel) 0 src / 1 dst*/ + uint8_t src_trans_mode; +}; diff --git a/drivers/video/rockchip/rga2/rga2_drv.c b/drivers/video/rockchip/rga2/rga2_drv.c index 3852d4460872..c0f4b438c22c 100755 --- a/drivers/video/rockchip/rga2/rga2_drv.c +++ b/drivers/video/rockchip/rga2/rga2_drv.c @@ -928,7 +928,7 @@ static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) static long compat_rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) { struct rga2_req req; - struct rga_req req_rga; + struct rga_req_32 req_rga; int ret = 0; rga2_session *session; @@ -952,26 +952,26 @@ static long compat_rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) switch (cmd) { case RGA_BLIT_SYNC: - if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req)))) + if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req_32)))) { ERR("copy_from_user failed\n"); ret = -EFAULT; break; } - RGA_MSG_2_RGA2_MSG(&req_rga, &req); + RGA_MSG_2_RGA2_MSG_32(&req_rga, &req); ret = rga2_blit_sync(session, &req); break; case RGA_BLIT_ASYNC: - if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req)))) + if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req_32)))) { ERR("copy_from_user failed\n"); ret = -EFAULT; break; } - RGA_MSG_2_RGA2_MSG(&req_rga, &req); + RGA_MSG_2_RGA2_MSG_32(&req_rga, &req); if((atomic_read(&rga2_service.total_running) > 8)) { diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.c b/drivers/video/rockchip/rga2/rga2_reg_info.c old mode 100644 new mode 100755 index e131181c25ff..06d0df818bd9 --- a/drivers/video/rockchip/rga2/rga2_reg_info.c +++ b/drivers/video/rockchip/rga2/rga2_reg_info.c @@ -1160,5 +1160,190 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req) } } - - +void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src) +{ + dst->yrgb_addr = src->yrgb_addr; /* yrgb mem addr */ + dst->uv_addr = src->uv_addr; /* cb/cr mem addr */ + dst->v_addr = src->v_addr; /* cr mem addr */ + dst->format = src->format; //definition by RK_FORMAT + + dst->act_w = src->act_w; + dst->act_h = src->act_h; + dst->x_offset = src->x_offset; + dst->y_offset = src->y_offset; + + dst->vir_w = src->vir_w; + dst->vir_h = src->vir_h; + dst->endian_mode = src->endian_mode; //for BPP + dst->alpha_swap = src->alpha_swap; +} +void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req) +{ + u16 alpha_mode_0, alpha_mode_1; + if (req_rga->render_mode == 6) + req->render_mode = update_palette_table_mode; + else if (req_rga->render_mode == 7) + req->render_mode = update_patten_buff_mode; + else if (req_rga->render_mode == 5) + req->render_mode = bitblt_mode; + else + req->render_mode = req_rga->render_mode; + memcpy_img_info(&req->src, &req_rga->src); + memcpy_img_info(&req->dst, &req_rga->dst); + memcpy_img_info(&req->pat, &req_rga->pat); + memcpy_img_info(&req->src1,&req_rga->pat); + format_name_convert(&req->src.format, req_rga->src.format); + format_name_convert(&req->dst.format, req_rga->dst.format); + if(req_rga->rotate_mode == 1) { + if(req_rga->sina == 0 && req_rga->cosa == 65536) { + req->rotate_mode = 0; + } + else if (req_rga->sina == 65536 && req_rga->cosa == 0) { + req->rotate_mode = 1; + req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_h + 1; + req->dst.act_w = req_rga->dst.act_h; + req->dst.act_h = req_rga->dst.act_w; + } + else if (req_rga->sina == 0 && req_rga->cosa == -65536) { + req->rotate_mode = 2; + req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_w + 1; + req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_h + 1; + } + else if (req_rga->sina == -65536 && req_rga->cosa == 0) { + req->rotate_mode = 3; + req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_w + 1; + req->dst.act_w = req_rga->dst.act_h; + req->dst.act_h = req_rga->dst.act_w; + } + } + else if (req_rga->rotate_mode == 2) + { + req->rotate_mode = (1 << 4); + } + else if (req_rga->rotate_mode == 3) + { + req->rotate_mode = (2 << 4); + } + else { + req->rotate_mode = 0; + } + if((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h)) + req->scale_bicu_mode |= (1<<4); + req->LUT_addr = req_rga->LUT_addr; + req->rop_mask_addr = req_rga->rop_mask_addr; + req->bitblt_mode = req_rga->bsfilter_flag; + req->src_a_global_val = req_rga->alpha_global_value; + req->dst_a_global_val = 0; + req->rop_code = req_rga->rop_code; + req->rop_mode = 0; + req->color_fill_mode = req_rga->color_fill_mode; + req->color_key_min = req_rga->color_key_min; + req->color_key_max = req_rga->color_key_max; + req->fg_color = req_rga->fg_color; + req->bg_color = req_rga->bg_color; + memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color)); + req->palette_mode = req_rga->palette_mode; + req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1; + req->endian_mode = req_rga->endian_mode; + req->rgb2yuv_mode = 0; + req->fading_alpha_value = 0; + req->fading_r_value = req_rga->fading.r; + req->fading_g_value = req_rga->fading.g; + req->fading_b_value = req_rga->fading.b; + req->alpha_rop_flag = 0; + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1))); // alpha_rop_enable + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1); // rop_enable + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2); // fading_enable + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3); // alpha_cal_mode_sel + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down + req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel + if(((req_rga->alpha_rop_flag) & 1)) { + if((req_rga->alpha_rop_flag >> 3) & 1) { + switch(req_rga->PD_mode) + { + case 0: //dst = 0 + break; + case 1: //dst = src + break; + case 2: //dst = dst + break; + case 3: //dst = (256*sc + (256 - sa)*dc) >> 8 + if((req_rga->alpha_rop_mode & 3) == 0) { + alpha_mode_0 = 0x3818; + alpha_mode_1 = 0x3818; + } + else if ((req_rga->alpha_rop_mode & 3) == 1) { + alpha_mode_0 = 0x381A; + alpha_mode_1 = 0x381A; + } + else if ((req_rga->alpha_rop_mode & 3) == 2) { + alpha_mode_0 = 0x381C; + alpha_mode_1 = 0x381C; + } + else { + alpha_mode_0 = 0x381A; + alpha_mode_1 = 0x381A; + } + req->alpha_mode_0 = alpha_mode_0; + req->alpha_mode_1 = alpha_mode_1; + break; + case 4: //dst = (sc*(256-da) + 256*dc) >> 8 + break; + case 5: //dst = (da*sc) >> 8 + break; + case 6: //dst = (sa*dc) >> 8 + break; + case 7: //dst = ((256-da)*sc) >> 8 + break; + case 8: //dst = ((256-sa)*dc) >> 8 + break; + case 9: //dst = (da*sc + (256-sa)*dc) >> 8 + req->alpha_mode_0 = 0x3848; + req->alpha_mode_1 = 0x3848; + break; + case 10://dst = ((256-da)*sc + (sa*dc)) >> 8 + break; + case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8; + break; + default: + break; + } + } + else { + if((req_rga->alpha_rop_mode & 3) == 0) { + req->alpha_mode_0 = 0x3848; + req->alpha_mode_1 = 0x3848; + } + else if ((req_rga->alpha_rop_mode & 3) == 1) { + req->alpha_mode_0 = 0x483A; + req->alpha_mode_1 = 0x483A; + } + else if ((req_rga->alpha_rop_mode & 3) == 2) { + req->alpha_mode_0 = 0x384C; + req->alpha_mode_1 = 0x384C; + } + } + } + if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) { + req->mmu_info.src0_mmu_flag = 1; + req->mmu_info.dst_mmu_flag = 1; + if (req_rga->mmu_info.mmu_flag >> 31) { + req->mmu_info.src0_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 8) & 1); + req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1); + req->mmu_info.dst_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 10) & 1); + req->mmu_info.els_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 11) & 1); + } + else { + if (req_rga->src.yrgb_addr >= 0xa0000000) { + req->mmu_info.src0_mmu_flag = 0; + req->src.yrgb_addr = req_rga->src.yrgb_addr - 0x60000000; + req->src.uv_addr = req_rga->src.uv_addr - 0x60000000; + req->src.v_addr = req_rga->src.v_addr - 0x60000000; + } + if (req_rga->dst.yrgb_addr >= 0xa0000000) { + req->mmu_info.dst_mmu_flag = 0; + req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000; + } + } + } +} diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.h b/drivers/video/rockchip/rga2/rga2_reg_info.h old mode 100644 new mode 100755 index 4751cde66d1e..b27046b462c9 --- a/drivers/video/rockchip/rga2/rga2_reg_info.h +++ b/drivers/video/rockchip/rga2/rga2_reg_info.h @@ -288,6 +288,7 @@ int RGA2_gen_reg_info(unsigned char *base, struct rga2_req *msg); void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req); +void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req);