From: Chris Lattner <sabre@nondot.org>
Date: Sat, 22 Dec 2007 20:47:56 +0000 (+0000)
Subject: Add a new FGETSIGN operation, which defaults to expand on all
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=1a3048bb8e0f3de0b4e56704c15c556c71565f4b;p=oota-llvm.git

Add a new FGETSIGN operation, which defaults to expand on all
targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45320 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 6490a0e05ac..d476ede5c29 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -271,6 +271,10 @@ namespace ISD {
     // FCOPYSIGN(f32, f64) is allowed.
     FCOPYSIGN,
 
+    // INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
+    // value as an integer 0/1 value.
+    FGETSIGN,
+    
     /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector
     /// with the specified, possibly variable, elements.  The number of elements
     /// is required to be a power of two.
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 2be31c82601..eed2d13187a 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -155,13 +155,17 @@ TargetLowering::TargetLowering(TargetMachine &tm)
   memset(&IndexedModeActions, 0, sizeof(IndexedModeActions));
   memset(&ConvertActions, 0, sizeof(ConvertActions));
 
-  // Set all indexed load / store to expand.
+  // Set default actions for various operations.
   for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
+    // Default all indexed load / store to expand.
     for (unsigned IM = (unsigned)ISD::PRE_INC;
          IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
       setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
       setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
     }
+    
+    // These operations default to expand.
+    setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
   }
 
   IsLittleEndian = TD->isLittleEndian();