From: Duncan Sands <baldrick@free.fr>
Date: Thu, 18 Feb 2010 14:37:52 +0000 (+0000)
Subject: Uniformize the way these options are printed.  Requested by
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=18619b2aeba5468512d6684c4fd96d0ad280e01d;p=oota-llvm.git

Uniformize the way these options are printed.  Requested by
Russell Wallace.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96580 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/docs/CommandGuide/lli.pod b/docs/CommandGuide/lli.pod
index 3d5da3d465a..6d1e1c65d43 100644
--- a/docs/CommandGuide/lli.pod
+++ b/docs/CommandGuide/lli.pod
@@ -170,7 +170,7 @@ Instruction schedulers available (before register allocation):
 
 =item B<-regalloc>=I<allocator>
 
-Register allocator to use: (default = linearscan)
+Register allocator to use (default=linearscan)
 
     =bigblock: Big-block register allocator 
     =linearscan: linear scan register allocator =local -   local register allocator 
@@ -186,7 +186,7 @@ Choose relocation model from:
 
 =item B<-spiller>
 
-Spiller to use: (default: local) 
+Spiller to use (default=local) 
 
     =simple: simple spiller 
     =local: local spiller 
diff --git a/docs/WritingAnLLVMPass.html b/docs/WritingAnLLVMPass.html
index 83de4f9b9de..f2be1fd3bbd 100644
--- a/docs/WritingAnLLVMPass.html
+++ b/docs/WritingAnLLVMPass.html
@@ -1630,7 +1630,7 @@ form; </p>
 <div class="doc_code"><pre>
 $ llc -help
   ...
-  -regalloc                    - Register allocator to use: (default = linearscan)
+  -regalloc                    - Register allocator to use (default=linearscan)
     =linearscan                -   linear scan register allocator
     =local                     -   local register allocator
     =simple                    -   simple register allocator
diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index f67eb79be3e..5ea2941b483 100644
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -34,7 +34,7 @@ static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
                RegisterPassParser<RegisterRegAlloc> >
 RegAlloc("regalloc",
          cl::init(&createLinearScanRegisterAllocator),
-         cl::desc("Register allocator to use: (default = linearscan)")); 
+         cl::desc("Register allocator to use (default=linearscan)")); 
 
 
 //===---------------------------------------------------------------------===//
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 84e03987a1c..7aa0a915352 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -46,7 +46,7 @@ namespace {
 
 static cl::opt<RewriterName>
 RewriterOpt("rewriter",
-            cl::desc("Rewriter to use: (default: local)"),
+            cl::desc("Rewriter to use (default=local)"),
             cl::Prefix,
             cl::values(clEnumVal(local,   "local rewriter"),
                        clEnumVal(trivial, "trivial rewriter"),
diff --git a/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td b/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td
index f13b9f8214f..33af18260f8 100644
--- a/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td
+++ b/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td
@@ -56,7 +56,7 @@ def OptionList : OptionList<[
 // (parameter_option "pre-RA-sched",
 //    (help "Example of an option that is passed to llc")),
  (parameter_option "regalloc",
-    (help "Register allocator to use.(possible values: simple, linearscan, pbqp, local. default = linearscan)")),
+    (help "Register allocator to use (possible values: simple, linearscan, pbqp, local; default=linearscan)")),
  (prefix_list_option "Wa,", (comma_separated),
     (help "Pass options to assembler (Run 'gpasm -help' for assembler options)")),
  (prefix_list_option "Wl,", (comma_separated),