From: Akira Hatanaka <ahatanak@gmail.com>
Date: Tue, 7 Jun 2011 19:28:39 +0000 (+0000)
Subject: Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=14487d4f66c3127b29408aae46c1a948d348ec59;p=oota-llvm.git

Refactor MipsTargetLowering::EmitInstrWithCustomInserter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132726 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index ccdcb34c047..92ab00bd36b 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -554,97 +554,11 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
   return Mips::BRANCH_INVALID;
 }
 
-MachineBasicBlock *
-MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
-                                                MachineBasicBlock *BB) const {
-  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
-  bool isFPCmp = false;
-  DebugLoc dl = MI->getDebugLoc();
-  unsigned Opc;
-
-  switch (MI->getOpcode()) {
-  default: assert(false && "Unexpected instr type to insert");
-
-  case Mips::ATOMIC_LOAD_ADD_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
-  case Mips::ATOMIC_LOAD_ADD_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
-  case Mips::ATOMIC_LOAD_ADD_I32:
-    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
-
-  case Mips::ATOMIC_LOAD_AND_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
-  case Mips::ATOMIC_LOAD_AND_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
-  case Mips::ATOMIC_LOAD_AND_I32:
-    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
-
-  case Mips::ATOMIC_LOAD_OR_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
-  case Mips::ATOMIC_LOAD_OR_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
-  case Mips::ATOMIC_LOAD_OR_I32:
-    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
-
-  case Mips::ATOMIC_LOAD_XOR_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
-  case Mips::ATOMIC_LOAD_XOR_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
-  case Mips::ATOMIC_LOAD_XOR_I32:
-    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
-
-  case Mips::ATOMIC_LOAD_NAND_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
-  case Mips::ATOMIC_LOAD_NAND_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
-  case Mips::ATOMIC_LOAD_NAND_I32:
-    return EmitAtomicBinary(MI, BB, 4, 0, true);
-
-  case Mips::ATOMIC_LOAD_SUB_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
-  case Mips::ATOMIC_LOAD_SUB_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
-  case Mips::ATOMIC_LOAD_SUB_I32:
-    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
-
-  case Mips::ATOMIC_SWAP_I8:
-    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
-  case Mips::ATOMIC_SWAP_I16:
-    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
-  case Mips::ATOMIC_SWAP_I32:
-    return EmitAtomicBinary(MI, BB, 4, 0);
-
-  case Mips::ATOMIC_CMP_SWAP_I8:
-    return EmitAtomicCmpSwapPartword(MI, BB, 1);
-  case Mips::ATOMIC_CMP_SWAP_I16:
-    return EmitAtomicCmpSwapPartword(MI, BB, 2);
-  case Mips::ATOMIC_CMP_SWAP_I32:
-    return EmitAtomicCmpSwap(MI, BB, 4);
-
-  case Mips::MOVT:
-  case Mips::MOVT_S:
-  case Mips::MOVT_D:
-    isFPCmp = true;
-    Opc = Mips::BC1F;
-    break;
-  case Mips::MOVF:
-  case Mips::MOVF_S:
-  case Mips::MOVF_D:
-    isFPCmp = true;
-    Opc = Mips::BC1T;
-    break;
-  case Mips::MOVZ_I:
-  case Mips::MOVZ_S:
-  case Mips::MOVZ_D:
-    Opc = Mips::BNE;
-    break;
-  case Mips::MOVN_I:
-  case Mips::MOVN_S:
-  case Mips::MOVN_D:
-    Opc = Mips::BEQ;
-    break;
-  }
-
+static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
+                                        DebugLoc dl,
+                                        const MipsSubtarget* Subtarget,
+                                        const TargetInstrInfo *TII,
+                                        bool isFPCmp, unsigned Opc) {
   // There is no need to expand CMov instructions if target has
   // conditional moves.
   if (Subtarget->hasCondMov())
@@ -688,7 +602,6 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
       .addReg(Mips::ZERO).addMBB(sinkMBB);
 
-
   //  copy0MBB:
   //   %FalseValue = ...
   //   # fallthrough to sinkMBB
@@ -717,6 +630,91 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   return BB;
 }
 
+MachineBasicBlock *
+MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
+                                                MachineBasicBlock *BB) const {
+  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+  DebugLoc dl = MI->getDebugLoc();
+
+  switch (MI->getOpcode()) {
+  default:
+    assert(false && "Unexpected instr type to insert");
+    return NULL;
+  case Mips::MOVT:
+  case Mips::MOVT_S:
+  case Mips::MOVT_D:
+    return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
+  case Mips::MOVF:
+  case Mips::MOVF_S:
+  case Mips::MOVF_D:
+    return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
+  case Mips::MOVZ_I:
+  case Mips::MOVZ_S:
+  case Mips::MOVZ_D:
+    return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
+  case Mips::MOVN_I:
+  case Mips::MOVN_S:
+  case Mips::MOVN_D:
+    return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
+
+  case Mips::ATOMIC_LOAD_ADD_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
+  case Mips::ATOMIC_LOAD_ADD_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
+  case Mips::ATOMIC_LOAD_ADD_I32:
+    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
+
+  case Mips::ATOMIC_LOAD_AND_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
+  case Mips::ATOMIC_LOAD_AND_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
+  case Mips::ATOMIC_LOAD_AND_I32:
+    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
+
+  case Mips::ATOMIC_LOAD_OR_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
+  case Mips::ATOMIC_LOAD_OR_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
+  case Mips::ATOMIC_LOAD_OR_I32:
+    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
+
+  case Mips::ATOMIC_LOAD_XOR_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
+  case Mips::ATOMIC_LOAD_XOR_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
+  case Mips::ATOMIC_LOAD_XOR_I32:
+    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
+
+  case Mips::ATOMIC_LOAD_NAND_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
+  case Mips::ATOMIC_LOAD_NAND_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
+  case Mips::ATOMIC_LOAD_NAND_I32:
+    return EmitAtomicBinary(MI, BB, 4, 0, true);
+
+  case Mips::ATOMIC_LOAD_SUB_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
+  case Mips::ATOMIC_LOAD_SUB_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
+  case Mips::ATOMIC_LOAD_SUB_I32:
+    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
+
+  case Mips::ATOMIC_SWAP_I8:
+    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
+  case Mips::ATOMIC_SWAP_I16:
+    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
+  case Mips::ATOMIC_SWAP_I32:
+    return EmitAtomicBinary(MI, BB, 4, 0);
+
+  case Mips::ATOMIC_CMP_SWAP_I8:
+    return EmitAtomicCmpSwapPartword(MI, BB, 1);
+  case Mips::ATOMIC_CMP_SWAP_I16:
+    return EmitAtomicCmpSwapPartword(MI, BB, 2);
+  case Mips::ATOMIC_CMP_SWAP_I32:
+    return EmitAtomicCmpSwap(MI, BB, 4);
+  }
+}
+
 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
 MachineBasicBlock *