From: Jim Grosbach Date: Fri, 25 Jun 2010 22:02:28 +0000 (+0000) Subject: 80 column and typo fix X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=135ec50ce26b4bb9aee305f5e861d2348969aa31;p=oota-llvm.git 80 column and typo fix git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106894 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 8d49212bf24..0b40d8e0389 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -951,7 +951,7 @@ static void UpdatePredRedefs(MachineInstr *MI, SmallSet &Redefs, if (AddImpUse) // Treat predicated update as read + write. MI->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, - true/*IsImp*/,false/*IsKill*/)); + true/*IsImp*/,false/*IsKill*/)); } else { Redefs.insert(Reg); for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) @@ -1205,7 +1205,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind, // Remove the conditional branch from entry to the blocks. BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); - // Initialize liveins to the first BB. These are potentiall redefined by + // Initialize liveins to the first BB. These are potentially redefined by // predicated instructions. SmallSet Redefs; InitPredRedefs(BBI1->BB, Redefs, TRI);