From: Jim Grosbach Date: Mon, 24 Oct 2011 22:16:58 +0000 (+0000) Subject: ARM assembly parsing and encoding for VLD1 w/ writeback. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=12431329d617064d6e72dd040a58c1635cc261ab;p=oota-llvm.git ARM assembly parsing and encoding for VLD1 w/ writeback. One and two length register list variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 9bea53b41a9..ff1a09a9ce7 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -325,6 +325,7 @@ multiclass VLD1DWB op7_4, string Dt> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDInstruction"; + let AsmMatchConverter = "cvtVLDwbFixed"; } def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u, @@ -332,6 +333,7 @@ multiclass VLD1DWB op7_4, string Dt> { "$Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDInstruction"; + let AsmMatchConverter = "cvtVLDwbRegister"; } } multiclass VLD1QWB op7_4, string Dt> { @@ -342,6 +344,7 @@ multiclass VLD1QWB op7_4, string Dt> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDInstruction"; + let AsmMatchConverter = "cvtVLDwbFixed"; } def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb), (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, @@ -349,6 +352,7 @@ multiclass VLD1QWB op7_4, string Dt> { "$Rn.addr = $wb", []> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDInstruction"; + let AsmMatchConverter = "cvtVLDwbRegister"; } } diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a13554f8826..a278f6fe57c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -198,6 +198,10 @@ class ARMAsmParser : public MCTargetAsmParser { const SmallVectorImpl &); bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); + bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, + const SmallVectorImpl &); + bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, + const SmallVectorImpl &); bool validateInstruction(MCInst &Inst, const SmallVectorImpl &Ops); @@ -3326,6 +3330,36 @@ cvtThumbMultiply(MCInst &Inst, unsigned Opcode, return true; } +bool ARMAsmParser:: +cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, + const SmallVectorImpl &Operands) { + // Vd + ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); + // Create a writeback register dummy placeholder. + Inst.addOperand(MCOperand::CreateImm(0)); + // Vn + ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); + // pred + ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); + return true; +} + +bool ARMAsmParser:: +cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, + const SmallVectorImpl &Operands) { + // Vd + ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); + // Create a writeback register dummy placeholder. + Inst.addOperand(MCOperand::CreateImm(0)); + // Vn + ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); + // Vm + ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); + // pred + ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); + return true; +} + /// Parse an ARM memory expression, return false if successful else return true /// or an error. The first token must be a '[' when called. bool ARMAsmParser:: diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index e01afeb7d30..ba45ea77248 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -17,22 +17,58 @@ vld1.32 {d5, d6, d7, d8}, [r3] vld1.64 {d6, d7, d8, d9}, [r3, :64] -@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] -@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] -@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] -@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] -@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] -@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] -@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] -@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] -@ CHECK: vld1.8 {d1, d2, d3}, [r3] @ encoding: [0x0f,0x16,0x23,0xf4] + vld1.8 {d16}, [r0, :64]! + vld1.16 {d16}, [r0]! + vld1.32 {d16}, [r0]! + vld1.64 {d16}, [r0]! + vld1.8 {d16, d17}, [r0, :64]! + vld1.16 {d16, d17}, [r0, :128]! + vld1.32 {d16, d17}, [r0]! + vld1.64 {d16, d17}, [r0]! + + vld1.8 {d16}, [r0, :64], r5 + vld1.16 {d16}, [r0], r5 + vld1.32 {d16}, [r0], r5 + vld1.64 {d16}, [r0], r5 + vld1.8 {d16, d17}, [r0, :64], r5 + vld1.16 {d16, d17}, [r0, :128], r5 + vld1.32 {d16, d17}, [r0], r5 + vld1.64 {d16, d17}, [r0], r5 + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] +@ CHECK: vld1.8 {d1, d2, d3}, [r3] @ encoding: [0x0f,0x16,0x23,0xf4] @ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4] -@ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4] @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4] -@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4] +@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4] @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4] @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3] @ encoding: [0x8f,0x52,0x23,0xf4] @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4] +@ CHECK: vld1.8 {d16}, [r0, :64]! @ encoding: [0x1d,0x07,0x60,0xf4] + +@ CHECK: vld1.16 {d16}, [r0]! @ encoding: [0x4d,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0]! @ encoding: [0x8d,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0]! @ encoding: [0xcd,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0]! @ encoding: [0x8d,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0]! @ encoding: [0xcd,0x0a,0x60,0xf4] + +@ CHECK: vld1.8 {d16}, [r0, :64], r5 @ encoding: [0x15,0x07,0x60,0xf4] +@ CHECK: vld1.16 {d16}, [r0], r5 @ encoding: [0x45,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0], r5 @ encoding: [0x85,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0], r5 @ encoding: [0xc5,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64], r5 @ encoding: [0x15,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128], r5 @ encoding: [0x65,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0], r5 @ encoding: [0x85,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0], r5 @ encoding: [0xc5,0x0a,0x60,0xf4] vld2.8 {d16, d17}, [r0, :64]