From: Bill Schmidt Date: Wed, 14 Jan 2015 20:17:10 +0000 (+0000) Subject: [PPC64] Add support for the ICBT instruction on POWER8. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=11abe69e9857390a035470c20534b8e5ac4d479e;hp=0a2caa143f0233bcf1ba04a358f3e21a095035e0;p=oota-llvm.git [PPC64] Add support for the ICBT instruction on POWER8. Patch by Kit Barton. Support for the ICBT instruction is currently present, but limited to embedded processors. This change adds a new FeatureICBT that can be used to identify whether the ICBT instruction is available on a specific processor. Two new tests are added: * Positive test to ensure the icbt instruction is present when using -mcpu=pwr8 * Negative test to ensure the icbt instruction is not generated when using -mcpu=pwr7 Both test cases use the Prefetch opcode in LLVM. They are based on the ppc64-prefetch.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226033 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index a7fd62c0730..82946373706 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -90,8 +90,11 @@ def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", "Enable the ldbrx instruction">; def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", "Enable the cmpb instruction">; +def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", + "Enable icbt instruction">; def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", - "Enable Book E instructions">; + "Enable Book E instructions", + [FeatureICBT]>; def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", "Has only the msync instruction instead of sync", [FeatureBookE]>; @@ -202,12 +205,12 @@ include "PPCInstrInfo.td" def : Processor<"generic", G3Itineraries, [Directive32]>; def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, - FeatureBookE, FeatureMSYNC, - DeprecatedMFTB]>; + FeatureICBT, FeatureBookE, + FeatureMSYNC, DeprecatedMFTB]>; def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, - FeatureBookE, FeatureMSYNC, - DeprecatedMFTB]>; + FeatureICBT, FeatureBookE, + FeatureMSYNC, DeprecatedMFTB]>; def : Processor<"601", G3Itineraries, [Directive601]>; def : Processor<"602", G3Itineraries, [Directive602]>; def : Processor<"603", G3Itineraries, [Directive603, @@ -247,14 +250,14 @@ def : ProcessorModel<"g5", G5Model, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"e500mc", PPCE500mcModel, [DirectiveE500mc, FeatureMFOCRF, - FeatureSTFIWX, FeatureBookE, FeatureISEL, - DeprecatedMFTB]>; + FeatureSTFIWX, FeatureICBT, FeatureBookE, + FeatureISEL, DeprecatedMFTB]>; def : ProcessorModel<"e5500", PPCE5500Model, [DirectiveE5500, FeatureMFOCRF, Feature64Bit, - FeatureSTFIWX, FeatureBookE, FeatureISEL, - DeprecatedMFTB]>; + FeatureSTFIWX, FeatureICBT, FeatureBookE, + FeatureISEL, DeprecatedMFTB]>; def : ProcessorModel<"a2", PPCA2Model, - [DirectiveA2, FeatureBookE, FeatureMFOCRF, + [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, @@ -262,7 +265,7 @@ def : ProcessorModel<"a2", PPCA2Model, FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, DeprecatedMFTB]>; def : ProcessorModel<"a2q", PPCA2Model, - [DirectiveA2, FeatureBookE, FeatureMFOCRF, + [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, @@ -319,7 +322,7 @@ def : ProcessorModel<"pwr8", P8Model, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, - Feature64Bit /*, Feature64BitRegs */, + Feature64Bit /*, Feature64BitRegs */, FeatureICBT, DeprecatedMFTB, DeprecatedDST]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : ProcessorModel<"ppc64", G5Model, diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index d597cdcbd64..a8b40c2afe1 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -681,7 +681,7 @@ def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; def IsE500 : Predicate<"PPCSubTarget->isE500()">; def HasSPE : Predicate<"PPCSubTarget->HasSPE()">; - +def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; //===----------------------------------------------------------------------===// // PowerPC Multiclass Definitions. @@ -1319,14 +1319,14 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", PPC970_DGroup_Single; def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), - "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>; + "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), (DCBT xoaddr:$dst)>; // data prefetch for loads def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), (DCBTST xoaddr:$dst)>; // data prefetch for stores def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), - (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read) + (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) // Atomic operations let usesCustomInserter = 1 in { diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index d8ba1c71a0f..ab36e90eaac 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -122,6 +122,8 @@ void PPCSubtarget::initializeEnvironment() { DeprecatedMFTB = false; DeprecatedDST = false; HasLazyResolverStubs = false; + HasICBT = false; + } void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index a1b644d2685..f5dc3003a7a 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -113,6 +113,7 @@ protected: bool DeprecatedDST; bool HasLazyResolverStubs; bool IsLittleEndian; + bool HasICBT; enum { PPC_ABI_UNKNOWN, @@ -230,6 +231,7 @@ public: bool isE500() const { return IsE500; } bool isDeprecatedMFTB() const { return DeprecatedMFTB; } bool isDeprecatedDST() const { return DeprecatedDST; } + bool hasICBT() const { return HasICBT; } const Triple &getTargetTriple() const { return TargetTriple; } diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll new file mode 100644 index 00000000000..e8617ccfc8a --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll @@ -0,0 +1,19 @@ +; Test the ICBT instruction is not emitted on POWER7 +; Based on the ppc64-prefetch.ll test +; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s + +declare void @llvm.prefetch(i8*, i32, i32, i32) + +define void @test(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0) + ret void + +; FIXME: Crashing is not really the correct behavior here, we really should just emit nothing +; CHECK: Cannot select: 0x{{[0-9,a-f]+}}: ch = Prefetch +; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<0> +; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<3> +; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<0> + +} + diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll new file mode 100644 index 00000000000..a0f084a6bf9 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll @@ -0,0 +1,16 @@ +; Test the ICBT instruction on POWER8 +; Copied from the ppc64-prefetch.ll test +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +declare void @llvm.prefetch(i8*, i32, i32, i32) + +define void @test(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0) + ret void + +; CHECK-LABEL: @test +; CHECK: icbt +} + +