From: James Molloy Date: Fri, 17 Apr 2015 13:51:40 +0000 (+0000) Subject: Fix TRUNCATE splitting helper logic. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=10331c740096c196b55f54a05d1a918bdea7dbfc;p=oota-llvm.git Fix TRUNCATE splitting helper logic. This is a followon to r233681 - I'd misunderstood the semantics of FTRUNC, and had confused it with (FP_ROUND ..., 0). Thanks for Ahmed Bougacha for his post-commit review! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235191 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 9de85d7e777..728def1c24d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -593,7 +593,7 @@ private: bool SplitVectorOperand(SDNode *N, unsigned OpNo); SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo); SDValue SplitVecOp_UnaryOp(SDNode *N); - SDValue SplitVecOp_TruncateHelper(SDNode *N, unsigned TruncateOp); + SDValue SplitVecOp_TruncateHelper(SDNode *N); SDValue SplitVecOp_BITCAST(SDNode *N); SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index f000902260e..f296edd254f 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1294,7 +1294,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; case ISD::TRUNCATE: - Res = SplitVecOp_TruncateHelper(N, ISD::TRUNCATE); + Res = SplitVecOp_TruncateHelper(N); break; case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; case ISD::STORE: @@ -1309,14 +1309,14 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0))) - Res = SplitVecOp_TruncateHelper(N, ISD::TRUNCATE); + Res = SplitVecOp_TruncateHelper(N); else Res = SplitVecOp_UnaryOp(N); break; case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0))) - Res = SplitVecOp_TruncateHelper(N, ISD::FTRUNC); + Res = SplitVecOp_TruncateHelper(N); else Res = SplitVecOp_UnaryOp(N); break; @@ -1327,10 +1327,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: case ISD::ANY_EXTEND: - Res = SplitVecOp_UnaryOp(N); - break; case ISD::FTRUNC: - Res = SplitVecOp_TruncateHelper(N, ISD::FTRUNC); + Res = SplitVecOp_UnaryOp(N); break; } } @@ -1595,8 +1593,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts); } -SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N, - unsigned TruncateOp) { +SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { // The result type is legal, but the input type is illegal. If splitting // ends up with the result type of each half still being legal, just // do that. If, however, that would result in an illegal result type, @@ -1618,6 +1615,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N, EVT InVT = InVec->getValueType(0); EVT OutVT = N->getValueType(0); unsigned NumElements = OutVT.getVectorNumElements(); + bool IsFloat = OutVT.isFloatingPoint(); + // Widening should have already made sure this is a power-two vector // if we're trying to split it at all. assert() that's true, just in case. assert(!(NumElements & 1) && "Splitting vector, but not in half!"); @@ -1636,7 +1635,9 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N, SDValue InLoVec, InHiVec; std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL); // Truncate them to 1/2 the element size. - EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2); + EVT HalfElementVT = IsFloat ? + EVT::getFloatingPointVT(InElementSize/2) : + EVT::getIntegerVT(*DAG.getContext(), InElementSize/2); EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements/2); SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); @@ -1649,7 +1650,10 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N, // type. This should normally be something that ends up being legal directly, // but in theory if a target has very wide vectors and an annoyingly // restricted set of legal types, this split can chain to build things up. - return DAG.getNode(TruncateOp, DL, OutVT, InterVec); + return IsFloat ? + DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, + DAG.getTargetConstant(0, TLI.getPointerTy())) : + DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec); } SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { diff --git a/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/test/CodeGen/AArch64/arm64-convert-v4f64.ll index c4e3e4eae63..b8da3991031 100644 --- a/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -31,3 +31,36 @@ define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ret <8 x i8> %tmp2 } +define <4 x half> @uitofp_v4i64_to_v4f16(<4 x i64>* %ptr) { +; CHECK: uitofp_v4i64_to_v4f16 +; CHECK-DAG: ucvtf v[[LHS:[0-9]+]].2d, v0.2d +; CHECK-DAG: ucvtf v[[RHS:[0-9]+]].2d, v1.2d +; CHECK-DAG: fcvtn v[[MID:[0-9]+]].2s, v[[LHS]].2d +; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d +; CHECK: fcvtn v0.4h, v[[MID]].4s + %tmp1 = load <4 x i64>, <4 x i64>* %ptr + %tmp2 = uitofp <4 x i64> %tmp1 to <4 x half> + ret <4 x half> %tmp2 +} + +define <4 x i16> @trunc_v4i64_to_v4i16(<4 x i64>* %ptr) { +; CHECK: trunc_v4i64_to_v4i16 +; CHECK: xtn +; CHECK: xtn2 +; CHECK: xtn + %tmp1 = load <4 x i64>, <4 x i64>* %ptr + %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16> + ret <4 x i16> %tmp2 +} + +define <4 x i16> @fptoui_v4f64_to_v4i16(<4 x double>* %ptr) { +; CHECK: fptoui_v4f64_to_v4i16 +; CHECK-DAG: fcvtzu v[[LHS:[0-9]+]].2d, v0.2d +; CHECK-DAG: fcvtzu v[[RHS:[0-9]+]].2d, v1.2d +; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d +; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d +; CHECK: xtn v0.4h, v[[MID]].4s + %tmp1 = load <4 x double>, <4 x double>* %ptr + %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16> + ret <4 x i16> %tmp2 +}