From: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri, 26 Jul 2013 19:03:48 +0000 (+0000)
Subject: [mips] Increase the number of floating point condition code registers to eight.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=0fc641df377bf6ea88bbc28b377f6a0810dfa220;p=oota-llvm.git

[mips] Increase the number of floating point condition code registers to eight.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 990aea45e9c..b9b934a4d3a 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -181,8 +181,9 @@ let Namespace = "Mips" in {
   foreach I = 0-31 in
   def FCR#I : MipsReg<#I, ""#I>;
 
-  // fcc0 register
-  def FCC0 : MipsReg<0, "fcc0">;
+  // FP condition code registers.
+  foreach I = 0-7 in
+  def FCC#I : MipsReg<#I, "fcc"#I>;
 
   // PC register
   def PC : Register<"pc">;
@@ -292,7 +293,8 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
           Unallocatable;
 
 // FP condition code registers.
-def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
+def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
+          Unallocatable;
 
 // Hi/Lo Registers
 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;