From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Fri, 8 Sep 2006 17:36:23 +0000 (+0000)
Subject: implement shl and sra
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=0a200600e777c8aac9646c9cba69693155a8142c;p=oota-llvm.git

implement shl and sra


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 892c297d8c6..c40521bed4d 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -113,6 +113,18 @@ def andrr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
 
+
+// All arm data processing instructions have a shift. Maybe we don't have
+// to implement this
+def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "mov $dst, $a, lsl $b",
+		       [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
+
+def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "mov $dst, $a, asr $b",
+		       [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
+
+
 def eor_rr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "eor $dst, $a, $b",
 		       [(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;
diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
new file mode 100644
index 00000000000..ca79e49829a
--- /dev/null
+++ b/test/CodeGen/ARM/bits.ll
@@ -0,0 +1,36 @@
+; RUN: llvm-as < %s | llc -march=arm &&
+; RUN: llvm-as < %s | llc -march=arm | grep and      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep orr      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep eor      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*asr | wc -l | grep 1
+
+int %f1(int %a, int %b) {
+entry:
+	%tmp2 = and int %b, %a		; <int> [#uses=1]
+	ret int %tmp2
+}
+
+int %f2(int %a, int %b) {
+entry:
+	%tmp2 = or int %b, %a		; <int> [#uses=1]
+	ret int %tmp2
+}
+
+int %f3(int %a, int %b) {
+entry:
+	%tmp2 = xor int %b, %a		; <int> [#uses=1]
+	ret int %tmp2
+}
+
+int %f4(int %a, ubyte %b) {
+entry:
+	%tmp3 = shl int %a, ubyte %b		; <int> [#uses=1]
+	ret int %tmp3
+}
+
+int %f5(int %a, ubyte %b) {
+entry:
+	%tmp3 = shr int %a, ubyte %b		; <int> [#uses=1]
+	ret int %tmp3
+}