From: Chris Lattner Date: Sun, 9 Oct 2005 05:58:56 +0000 (+0000) Subject: When emiting a CopyFromReg and the source is already a vreg, do not bother X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=089c25ccb3469946d70d9fa97d2e0b7ab16902a2;p=oota-llvm.git When emiting a CopyFromReg and the source is already a vreg, do not bother creating a new vreg and inserting a copy: just use the input vreg directly. This speeds up the compile (e.g. about 5% on mesa with a debug build of llc) by not adding a bunch of copies and vregs to be coallesced away. On mesa, for example, this reduces the number of intervals from 168601 to 129040 going into the coallescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23671 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 4b81c9a4c66..742304187de 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -1025,22 +1025,23 @@ void SimpleSched::EmitNode(NodeInfo *NI) { } case ISD::CopyFromReg: { unsigned SrcReg = cast(Node->getOperand(1))->getReg(); - - // Figure out the register class to create for the destreg. - const TargetRegisterClass *TRC = 0; if (MRegisterInfo::isVirtualRegister(SrcReg)) { - TRC = RegMap->getRegClass(SrcReg); - } else { - // Pick the register class of the right type that contains this physreg. - for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), - E = MRI.regclass_end(); I != E; ++I) - if ((*I)->getType() == Node->getValueType(0) && - (*I)->contains(SrcReg)) { - TRC = *I; - break; - } - assert(TRC && "Couldn't find register class for reg copy!"); + VRBase = SrcReg; // Just use the input register directly! + break; } + + // Figure out the register class to create for the destreg. + const TargetRegisterClass *TRC = 0; + + // Pick the register class of the right type that contains this physreg. + for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), + E = MRI.regclass_end(); I != E; ++I) + if ((*I)->getType() == Node->getValueType(0) && + (*I)->contains(SrcReg)) { + TRC = *I; + break; + } + assert(TRC && "Couldn't find register class for reg copy!"); // Create the reg, emit the copy. VRBase = RegMap->createVirtualRegister(TRC); @@ -1206,21 +1207,24 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) { EmitDAG(Op.getOperand(0)); // Emit the chain. unsigned SrcReg = cast(Op.getOperand(1))->getReg(); + // If the input is already a virtual register, just use it. + if (MRegisterInfo::isVirtualRegister(SrcReg)) { + ResultReg = SrcReg; + break; + } + // Figure out the register class to create for the destreg. const TargetRegisterClass *TRC = 0; - if (MRegisterInfo::isVirtualRegister(SrcReg)) { - TRC = RegMap->getRegClass(SrcReg); - } else { - // Pick the register class of the right type that contains this physreg. - for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), - E = MRI.regclass_end(); I != E; ++I) - if ((*I)->getType() == Op.Val->getValueType(0) && - (*I)->contains(SrcReg)) { - TRC = *I; - break; - } - assert(TRC && "Couldn't find register class for reg copy!"); - } + + // Pick the register class of the right type that contains this physreg. + for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), + E = MRI.regclass_end(); I != E; ++I) + if ((*I)->getType() == Op.Val->getValueType(0) && + (*I)->contains(SrcReg)) { + TRC = *I; + break; + } + assert(TRC && "Couldn't find register class for reg copy!"); // Create the reg, emit the copy. ResultReg = RegMap->createVirtualRegister(TRC);