From: Owen Anderson <resistor@mac.com>
Date: Wed, 12 Sep 2012 20:09:19 +0000 (+0000)
Subject: Remove an overly-aggressive assertion.  The code following this assertion already... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=045ca86bb3494e60ec2be72cabb5683fe204d066;p=oota-llvm.git

Remove an overly-aggressive assertion.  The code following this assertion already knows how to handle the case where DstRC was NULL, so it's not actually protecting us from anything, and this pattern can come up when using unknown_class operands in the SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163736 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 6d2cdeabd15..f6c164013d6 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -314,8 +314,6 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
     const TargetRegisterClass *DstRC = 0;
     if (IIOpNum < II->getNumOperands())
       DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
-    assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
-           "Don't have operand info for this instruction!");
     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
       unsigned NewVReg = MRI->createVirtualRegister(DstRC);
       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),