From: Dan Gohman Date: Mon, 1 Mar 2010 17:59:21 +0000 (+0000) Subject: Fix optimization of ISD::TRUNCATE on vector operands. Based on a patch X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=042919c0c5f87f937e1a01ca548811af2f297e83;p=oota-llvm.git Fix optimization of ISD::TRUNCATE on vector operands. Based on a patch by Micah Villmow for PR6335. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97461 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 2762ce8d57c..eca9f3f1c88 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1441,8 +1441,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, case ISD::TRUNCATE: { // Simplify the input, using demanded bit information, and compute the known // zero/one bits live out. + unsigned OperandBitWidth = + Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); APInt TruncMask = NewMask; - TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); + TruncMask.zext(OperandBitWidth); if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, KnownZero, KnownOne, TLO, Depth+1)) return true; @@ -1453,15 +1455,14 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // on the known demanded bits. if (Op.getOperand(0).getNode()->hasOneUse()) { SDValue In = Op.getOperand(0); - unsigned InBitWidth = In.getValueSizeInBits(); switch (In.getOpcode()) { default: break; case ISD::SRL: // Shrink SRL by a constant if none of the high bits shifted in are // demanded. if (ConstantSDNode *ShAmt = dyn_cast(In.getOperand(1))){ - APInt HighBits = APInt::getHighBitsSet(InBitWidth, - InBitWidth - BitWidth); + APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, + OperandBitWidth - BitWidth); HighBits = HighBits.lshr(ShAmt->getZExtValue()); HighBits.trunc(BitWidth);