From: Mark Yao Date: Fri, 17 Mar 2017 01:36:32 +0000 (+0800) Subject: arm64: dts: rk3368: don't assign clock rates for display pll X-Git-Tag: firefly_0821_release~301 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=03b9791af318ad3d3f5b5e57e3a88c6f758b3038;p=firefly-linux-kernel-4.4.55.git arm64: dts: rk3368: don't assign clock rates for display pll NPLL is used for display pixelclock, assign clock rates would overlap loader pll setting, cause display abnormal. Change-Id: Iaf1094c43526c7ca7b364608fa7153d03f84326c Signed-off-by: Mark Yao --- diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 19913eaa00e7..c3a29e31c953 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -1045,13 +1045,11 @@ #reset-cells = <1>; assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_BUS>, <&cru ACLK_PERI>, <&cru HCLK_BUS>, <&cru HCLK_PERI>, <&cru PCLK_BUS>, <&cru PCLK_PERI>; assigned-clock-rates = <576000000>, <400000000>, - <1188000000>, <300000000>, <300000000>, <150000000>, <150000000>, <75000000>, <75000000>;