From: Chris Lattner <sabre@nondot.org>
Date: Tue, 16 Nov 2010 00:57:32 +0000 (+0000)
Subject: add copy of comment to the code that will survive the mcjit'ization
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=0382a4c98ea8a73cbe2232d71b4bf1303d718274;p=oota-llvm.git

add copy of comment to the code that will survive the mcjit'ization


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119308 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
index b4a1b19d8a1..f286b27d5d1 100644
--- a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
@@ -199,6 +199,8 @@ unsigned PPCMCCodeEmitter::
 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups) const {
   if (MO.isReg()) {
+    // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
+    // The GPR operand should come through here though.
     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
     return PPCRegisterInfo::getRegisterNumbering(MO.getReg());