From: Akira Hatanaka <ahatanaka@mips.com>
Date: Thu, 16 May 2013 19:57:23 +0000 (+0000)
Subject: [mips] Test case for r182042. Add comment.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=02e168003f45cf8e0a277c6b8c85c1a3032b1dec;p=oota-llvm.git

[mips] Test case for r182042. Add comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182044 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h
index f4c29b1676a..e44ff42b706 100644
--- a/lib/Target/Mips/MipsSEInstrInfo.h
+++ b/lib/Target/Mips/MipsSEInstrInfo.h
@@ -83,9 +83,21 @@ private:
 
   void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    unsigned Opc) const;
+
+  /// Expand pseudo Int-to-FP conversion instructions.
+  ///
+  /// For example, the following pseudo instruction
+  ///  PseudoCVT_D32_W D2, A5
+  /// gets expanded into these two instructions:
+  ///  MTC1 F4, A5
+  ///  CVT_D32_W D2, F4
+  ///
+  /// We do this expansion post-RA to avoid inserting a floating point copy
+  /// instruction between MTC1 and CVT_D32_W.
   void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                       unsigned CvtOpc, unsigned MovOpc, bool DstIsLarger,
                       bool SrcIsLarger, bool IsI64) const;
+
   void expandExtractElementF64(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I) const;
   void expandBuildPairF64(MachineBasicBlock &MBB,
diff --git a/test/CodeGen/Mips/int-to-float-conversion.ll b/test/CodeGen/Mips/int-to-float-conversion.ll
new file mode 100644
index 00000000000..2a7dfdd68b3
--- /dev/null
+++ b/test/CodeGen/Mips/int-to-float-conversion.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+
+@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
+@i3 = common global i32* null, align 4
+
+; 32: test_float_int_:
+; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
+
+define float @test_float_int_(i32 %a) {
+entry:
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+; 32: test_double_int_:
+; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
+; 64: test_double_int_:
+; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
+
+define double @test_double_int_(i32 %a) {
+entry:
+  %conv = sitofp i32 %a to double
+  ret double %conv
+}
+
+; 64: test_float_LL_:
+; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
+
+define float @test_float_LL_(i64 %a) {
+entry:
+  %conv = sitofp i64 %a to float
+  ret float %conv
+}
+
+; 64: test_double_LL_:
+; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
+
+define double @test_double_LL_(i64 %a) {
+entry:
+  %conv = sitofp i64 %a to double
+  ret double %conv
+}