From: Evan Cheng Date: Wed, 10 Sep 2008 20:08:45 +0000 (+0000) Subject: Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machin... X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=014264b70f2af002a41f8e36a9430fcf20e77bc7;p=oota-llvm.git Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56065 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 4fd0ad44b05..e783e04a616 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -832,8 +832,10 @@ namespace { } Spills.ClobberPhysReg(NewPhysReg); Spills.ClobberPhysReg(NewOp.PhysRegReused); - - MI->getOperand(NewOp.Operand).setReg(NewPhysReg); + + unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg(); + unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; + MI->getOperand(NewOp.Operand).setReg(RReg); Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); --MII;