From: Mon P Wang <wangmp@apple.com>
Date: Tue, 11 Nov 2008 05:40:06 +0000 (+0000)
Subject: Cleaned up and fix bugs in convert_rndsat node
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=00ec49b6bafc33ee17d97ec1c723e1edb41d4c97;p=oota-llvm.git

Cleaned up and fix bugs in convert_rndsat node


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59025 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 5c87e044b0f..94bb2ae79b8 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -432,9 +432,10 @@ namespace ISD {
     BIT_CONVERT,
     
     // CONVERT_RNDSAT - This operator is used to support various conversions
-    // between various types (float, signed, unsigned) with rounding and
-    // saturation. NOTE: Avoid using this operator as most target don't support
-    // it and they might be removed. It takes the following arguments:
+    // between various types (float, signed, unsigned and vectors of those
+    // types) with rounding and saturation. NOTE: Avoid using this operator as
+    // most target don't support it and the operator might be removed in the
+    // future. It takes the following arguments:
     //   0) value
     //   1) dest type (type to convert to)
     //   2) src type (type to convert from)
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0a579de91e5..508fb4802ae 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -59,6 +59,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::BSWAP:       Result = PromoteIntRes_BSWAP(N); break;
   case ISD::BUILD_PAIR:  Result = PromoteIntRes_BUILD_PAIR(N); break;
   case ISD::Constant:    Result = PromoteIntRes_Constant(N); break;
+  case ISD::CONVERT_RNDSAT:
+                         Result = PromoteIntRes_CONVERT_RNDSAT(N); break;
   case ISD::CTLZ:        Result = PromoteIntRes_CTLZ(N); break;
   case ISD::CTPOP:       Result = PromoteIntRes_CTPOP(N); break;
   case ISD::CTTZ:        Result = PromoteIntRes_CTTZ(N); break;
@@ -272,6 +274,41 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
   return Result;
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
+  ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
+  assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
+           CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
+           CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
+          "can only promote integers");
+  SDValue InOp = N->getOperand(0);
+
+  MVT InVT = InOp.getValueType();
+  MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
+  switch (getTypeAction(InVT)) {
+  default:
+    assert(false && "Unknown type action!");
+    break;
+  case Legal:
+    break;
+  case PromoteInteger:
+    return DAG.getConvertRndSat(OutVT, GetPromotedInteger(InOp),
+                                N->getOperand(1), N->getOperand(2),
+                                N->getOperand(3), N->getOperand(4), CvtCode);
+    break;
+  case SoftenFloat:
+  case ExpandInteger:
+  case ExpandFloat:
+    break;
+  case ScalarizeVector:
+  case SplitVector:
+    assert(false && "can not convert a vector to a scalar!");
+  }
+  return DAG.getConvertRndSat(OutVT, InOp,
+                              N->getOperand(1), N->getOperand(2),
+                              N->getOperand(3), N->getOperand(4), CvtCode);
+}
+
+
 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   MVT OVT = N->getValueType(0);
@@ -610,8 +647,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
     case ISD::ZERO_EXTEND:  Res = PromoteIntOp_ZERO_EXTEND(N); break;
 
     case ISD::SINT_TO_FP:
-    case ISD::UINT_TO_FP:      Res = PromoteIntOp_INT_TO_FP(N); break;
-    case ISD::CONVERT_RNDSAT:  Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
+    case ISD::UINT_TO_FP:     Res = PromoteIntOp_INT_TO_FP(N); break;
     }
   }
 
@@ -814,21 +850,6 @@ SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
   return DAG.UpdateNodeOperands(SDValue(N, 0), In);
 }
 
-SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
-  MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
-  ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
-  assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
-           CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
-           CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
-          "can only promote integers");
-  SDValue In = DAG.getConvertRndSat(OutVT,N->getOperand(0),
-                                    N->getOperand(1), N->getOperand(2),
-                                    N->getOperand(3), N->getOperand(4), CvtCode);
-  return DAG.UpdateNodeOperands(SDValue(N, 0), In);
-}
-
-
-
 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
   SDValue NewOps[6];
   NewOps[0] = N->getOperand(0);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index a69302add72..ebba481902e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -231,6 +231,7 @@ private:
   SDValue PromoteIntRes_BSWAP(SDNode *N);
   SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
   SDValue PromoteIntRes_Constant(SDNode *N);
+  SDValue PromoteIntRes_CONVERT_RNDSAT(SDNode *N);
   SDValue PromoteIntRes_CTLZ(SDNode *N);
   SDValue PromoteIntRes_CTPOP(SDNode *N);
   SDValue PromoteIntRes_CTTZ(SDNode *N);
@@ -259,7 +260,6 @@ private:
   SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
-  SDValue PromoteIntOp_CONVERT_RNDSAT(SDNode *N);
   SDValue PromoteIntOp_FP_EXTEND(SDNode *N);
   SDValue PromoteIntOp_FP_ROUND(SDNode *N);
   SDValue PromoteIntOp_INT_TO_FP(SDNode *N);