#include <linux/miscdevice.h>\r
\r
#define SPI_FPGA_INT_PIN RK2818_PIN_PA4\r
-#define SPI_DPRAM_BUSY_PIN RK2818_PIN_PA2\r
+#define SPI_DPRAM_INT_PIN RK2818_PIN_PA2\r
#define SPI_FPGA_STANDBY_PIN RK2818_PIN_PH7\r
-#define SPI_FPGA_RST_PIN RK2818_PIN_PH6\r
+#define SPI_FPGA_RST_PIN RK2818_PIN_PF4\r
\r
#define SPI_FPGA_TEST_DEBUG 0\r
#if SPI_FPGA_TEST_DEBUG\r
{\r
struct workqueue_struct *spi_dpram_workqueue;\r
struct work_struct spi_dpram_work; \r
- struct workqueue_struct *spi_dpram_busy_workqueue;\r
- struct work_struct spi_dpram_busy_work;\r
+ struct workqueue_struct *spi_dpram_irq_workqueue;\r
+ struct work_struct spi_dpram_irq_work;\r
struct timer_list dpram_timer;\r
unsigned char *prx;\r
unsigned char *ptx;\r
int (*read_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);\r
int (*write_ptr)(struct spi_dpram *, unsigned short int addr, unsigned int size);\r
int (*read_ptr)(struct spi_dpram *, unsigned short int addr);\r
- int (*write_mailbox)(struct spi_dpram *, unsigned int mailbox);\r
- int (*read_mailbox)(struct spi_dpram *);\r
+ int (*write_irq)(struct spi_dpram *, unsigned int mailbox);\r
+ int (*read_irq)(struct spi_dpram *);\r
+ int (*write_ack)(struct spi_dpram *, unsigned int mailbox);\r
+ int (*read_ack)(struct spi_dpram *);\r
\r
};\r
\r
struct spi_fpga_port {\r
const char *name;\r
struct spi_device *spi;\r
+ spinlock_t work_lock;\r
struct mutex spi_lock;\r
struct workqueue_struct *fpga_irq_workqueue;\r
struct work_struct fpga_irq_work; \r
extern int spi_i2c_unregister(struct spi_fpga_port *port);\r
#endif\r
#if defined(CONFIG_SPI_FPGA_DPRAM)\r
-extern int spi_dpram_handle_irq(struct spi_device *spi);\r
+extern int spi_dpram_handle_ack(struct spi_device *spi);\r
extern int spi_dpram_register(struct spi_fpga_port *port);\r
extern int spi_dpram_unregister(struct spi_fpga_port *port);\r
#endif\r
#endif\r
\r
#define SPI_DPRAM_TEST 0\r
+\r
/*****RAM0 for bp write and ap read*****/\r
#define SPI_DPRAM_BPWRITE_START 0\r
#define SPI_DPRAM_BPWRITE_END 0x0fff\r
#define SPI_DPRAM_LOG_APWRITE_END 0x33ff\r
#define SPI_DPRAM_LOG_APWRITE_SIZE 0x0400 // 1K*16bits\r
\r
-/*\r
-#define BP_SEND_IN_PTR 0x3FEE\r
-#define BP_SEND_OUT_PTR 0x3FF0\r
-\r
-#define BP_READ_IN_PTR 0x3FF2\r
-#define BP_READ_OUT_PTR 0x3FF4\r
-\r
-#define BP_SEND_IN_PTR 0x3FF6\r
-#define BP_SEND_OUT_PTR 0x3FF8\r
-\r
-#define BP_READ_IN_PTR 0x3FFA\r
-#define BP_READ_OUT_PTR 0x3FFC\r
-\r
-#define BP_SEND_AP_Mailbox£º0x3ffe\r
-#define AP_SEND_BP_Mailbox£º0x3fff\r
-\r
-*/\r
\r
#define SPI_DPRAM_PTR0_BPWRITE_APREAD 0X3fee\r
#define SPI_DPRAM_PTR0_APWRITE_BPREAD 0X3ff0\r
#define SPI_DPRAM_PTR3_BPWRITE_APREAD 0x3ffa\r
#define SPI_DPRAM_PTR3_APWRITE_BPREAD 0x3ffc\r
\r
-#define SPI_DPRAM_MAILBOX_BPWRITE 0x3ffe\r
-#define SPI_DPRAM_MAILBOX_APWRITE 0x3fff\r
+#define SPI_DPRAM_MAILBOX_BPIRQ 0x3ffe\r
+#define SPI_DPRAM_MAILBOX_APIRQ 0x3fff\r
+#define SPI_DPRAM_MAILBOX_BPACK 0x3ffb\r
+#define SPI_DPRAM_MAILBOX_APACK 0x3ffd\r
\r
/*mailbox comminication's definition*/\r
-#define MAILBOX_BPWRITE_DATA 0x01\r
-#define MAILBOX_BPREAD_DATA 0x02\r
-#define MAILBOX_APSEND_IRQ 0x03\r
-#define MAILBOX_APSEND_ACK 0x04\r
-\r
+#define MAILBOX_BPSEND_IRQ (0<<15)\r
+#define MAILBOX_BPSEND_ACK (1<<15)\r
+#define MAILBOX_APSEND_IRQ (0<<15)\r
+#define MAILBOX_APSEND_ACK (1<<15)\r
+#define MAILBOX_RAM0 (0<<13)\r
+#define MAILBOX_RAM1 (1<<13)\r
+#define MAILBOX_RAM2 (2<<13)\r
+#define MAILBOX_RAM3 (3<<13)\r
+\r
+#define PIN_BPSEND_ACK RK2818_PIN_PE0\r
+#define PIN_APSEND_ACK RK2818_PIN_PF7\r
+\r
+#define MAX_SPI_LEN 768 //the bytes of spi write or read one time\r
#define TRUE 1\r
#define FALSE 0\r
\r
{ \r
struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram);\r
unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL) | ICE_SEL_DPRAM_WRITE);\r
- unsigned char *tx_buf = port->dpram.ptx; \r
- int ret;\r
- *(port->dpram.ptx) = opt;\r
- *(port->dpram.ptx+1) = ((addr << 1) >> 8) & 0xff;\r
- *(port->dpram.ptx+2) = ((addr << 1) & 0xff);\r
- memcpy((port->dpram.ptx + 3), buf, len);\r
+ unsigned char tx_buf[MAX_SPI_LEN+3];\r
+ int i,ret,mod,num,count;\r
+\r
+#if 0\r
+ unsigned char *p = buf;\r
+ for(i=0;i<len;i++)\r
+ {\r
+ printk("%s:buf[%d]=0x%x\n",__FUNCTION__,i,*p);\r
+ p++;\r
+ }\r
+#endif\r
+\r
+ mod = len%MAX_SPI_LEN;\r
+ if(!mod)\r
+ num = len/MAX_SPI_LEN;\r
+ else\r
+ num = len/MAX_SPI_LEN + 1;\r
+\r
+ for(i=0;i<num;i++)\r
+ { \r
+ if(i == num -1)\r
+ {\r
+ if(!mod)\r
+ count = MAX_SPI_LEN;\r
+ else\r
+ count = mod; \r
+ memcpy(tx_buf + 3, buf+i*MAX_SPI_LEN, count);\r
+ }\r
+ else\r
+ {\r
+ count = MAX_SPI_LEN;\r
+ memcpy(tx_buf + 3, buf+i*MAX_SPI_LEN, count);\r
+ }\r
+\r
+ tx_buf[0] = opt;\r
+ tx_buf[1] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) >> 8) & 0xff;\r
+ tx_buf[2] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) & 0xff);\r
+ ret = spi_write(port->spi, tx_buf, count+3);\r
+ if(ret)\r
+ {\r
+ printk("%s:spi_write err! i=%d\n",__FUNCTION__,i);\r
+ return ret;\r
+ }\r
+ }\r
\r
- DBG("%s:tx_buf=0x%x,port->dpram.ptx=0x%x,opt=0x%x,addr=0x%x,len=%d\n",__FUNCTION__,(int)tx_buf, (int)port->dpram.ptx, opt, addr&0xffff, len);\r
- ret = spi_write(port->spi, tx_buf, len+3);\r
- if(ret)\r
- printk("spi_write err!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");\r
return 0;\r
}\r
\r
unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL & ICE_SEL_DPRAM_READ));\r
unsigned char tx_buf[4];\r
unsigned char stat;\r
+ int i,mod,num,count;\r
\r
- tx_buf[0] = opt;\r
- tx_buf[1] = ((addr << 1) >> 8) & 0xff;\r
- tx_buf[2] = ((addr << 1) & 0xff);\r
- tx_buf[3] = 0;//give fpga 8 clks for reading data\r
- \r
- stat = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), buf, len); \r
- if(stat)\r
+ mod = len%MAX_SPI_LEN;\r
+ if(!mod)\r
+ num = len/MAX_SPI_LEN;\r
+ else\r
+ num = len/MAX_SPI_LEN + 1;\r
+\r
+ for(i=0;i<num;i++)\r
{\r
- printk("%s:spi_write_then_read is error!,err=%d\n\n",__FUNCTION__,stat);\r
- return -1;\r
+ if(i == num -1)\r
+ {\r
+ if(!mod)\r
+ count = MAX_SPI_LEN;\r
+ else\r
+ count = mod; \r
+ }\r
+ else\r
+ {\r
+ count = MAX_SPI_LEN;\r
+ }\r
+ \r
+ tx_buf[0] = opt;\r
+ tx_buf[1] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) >> 8) & 0xff;\r
+ tx_buf[2] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) & 0xff);\r
+ tx_buf[3] = 0;//give fpga 8 clks for reading data\r
+\r
+ stat = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), buf + i*MAX_SPI_LEN, count); \r
+ if(stat)\r
+ {\r
+ printk("%s:spi_write_then_read is error!,err=%d\n\n",__FUNCTION__,stat);\r
+ return -1;\r
+ }\r
+\r
}\r
- DBG("%s:opt=0x%x,addr=0x%x,len=%d\n",__FUNCTION__, opt, addr&0xffff, len);\r
+ \r
return 0;\r
\r
}\r
\r
\r
-int spi_dpram_write_ptr(struct spi_dpram *dpram, unsigned short int addr, unsigned int size)\r
+int spi_dpram_write_word(struct spi_dpram *dpram, unsigned short int addr, unsigned int size)\r
{\r
int ret;\r
//int i;\r
}\r
\r
\r
-int spi_dpram_read_ptr(struct spi_dpram *dpram, unsigned short int addr)\r
+int spi_dpram_read_word(struct spi_dpram *dpram, unsigned short int addr)\r
{\r
int ret;\r
struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram);\r
\r
}\r
\r
+int spi_dpram_write_ptr(struct spi_dpram *dpram, unsigned short int addr, unsigned int size)\r
+{\r
+ return spi_dpram_write_word(dpram, addr, size);\r
+}\r
+\r
\r
-int spi_dpram_write_mailbox(struct spi_dpram *dpram, unsigned int mailbox)\r
+int spi_dpram_read_ptr(struct spi_dpram *dpram, unsigned short int addr)\r
{\r
- int ret;\r
- struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram);\r
- unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL) | ICE_SEL_DPRAM_WRITE);\r
- unsigned char tx_buf[5];\r
- \r
- tx_buf[0] = opt;\r
- tx_buf[1] = ((SPI_DPRAM_MAILBOX_APWRITE << 1) >> 8) & 0xff;\r
- tx_buf[2] = ((SPI_DPRAM_MAILBOX_APWRITE << 1) & 0xff);\r
- tx_buf[3] = mailbox>>8;\r
- tx_buf[4] = mailbox&0xff;\r
- \r
- ret = spi_write(port->spi, tx_buf, sizeof(tx_buf));\r
- if(ret)\r
- {\r
- printk("%s:spi_write err!\n",__FUNCTION__);\r
- return -1;\r
- }\r
- \r
- return 0;\r
+ return spi_dpram_read_word(dpram, addr);\r
}\r
\r
\r
-int spi_dpram_read_mailbox(struct spi_dpram *dpram)\r
+int spi_dpram_write_irq(struct spi_dpram *dpram, unsigned int mailbox)\r
{\r
- int ret;\r
- struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram);\r
- unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL & ICE_SEL_DPRAM_READ));\r
- unsigned char tx_buf[4],rx_buf[2];\r
- \r
- tx_buf[0] = opt;\r
- tx_buf[1] = ((SPI_DPRAM_MAILBOX_BPWRITE << 1) >> 8) & 0xff;\r
- tx_buf[2] = ((SPI_DPRAM_MAILBOX_BPWRITE << 1) & 0xff);\r
- tx_buf[3] = 0;//give fpga 8 clks for reading data\r
+ return spi_dpram_write_word(dpram, SPI_DPRAM_MAILBOX_APIRQ,mailbox);\r
+}\r
\r
- ret = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), rx_buf, sizeof(rx_buf));\r
- if(ret)\r
- {\r
- printk("%s:spi_write_then_read err!\n",__FUNCTION__);\r
- return -1;\r
- }\r
- \r
- return ((rx_buf[0]<<8) | rx_buf[1]);\r
+\r
+int spi_dpram_read_irq(struct spi_dpram *dpram)\r
+{\r
+ return spi_dpram_read_word(dpram, SPI_DPRAM_MAILBOX_BPIRQ);\r
}\r
\r
+int spi_dpram_write_ack(struct spi_dpram *dpram, unsigned int mailbox)\r
+{\r
+ return spi_dpram_write_word(dpram, SPI_DPRAM_MAILBOX_APACK,mailbox);\r
+}\r
\r
-static void spi_dpram_handle_busy(struct spi_device *spi)\r
-{ \r
\r
+int spi_dpram_read_ack(struct spi_dpram *dpram)\r
+{\r
+ return spi_dpram_read_word(dpram, SPI_DPRAM_MAILBOX_BPACK);\r
}\r
\r
+int gNumSendInt=0,gLastNumSendInt = 0;\r
+int gNumSendAck=0,gLastNumSendAck = 0;\r
+int gNumRecInt=0,gNumLastRecInt = 0;\r
+int gNumCount = 0;\r
+unsigned char buf_dpram[SPI_DPRAM_BPWRITE_SIZE<<1];\r
\r
-static void spi_dpram_busy_work_handler(struct work_struct *work)\r
+\r
+//really is spi_dpram_irq_work_handler after dpram's pin is exchanged \r
+static void spi_dpram_irq_work_handler(struct work_struct *work)\r
{\r
struct spi_fpga_port *port =\r
- container_of(work, struct spi_fpga_port, dpram.spi_dpram_busy_work);\r
- spi_dpram_handle_busy(port->spi);\r
-}\r
+ container_of(work, struct spi_fpga_port, dpram.spi_dpram_irq_work);\r
+ \r
+ unsigned short int mbox = port->dpram.read_irq(&port->dpram);\r
+ unsigned int ptr;\r
+ unsigned int len;\r
+ //int i,ret;\r
+\r
+ //gNumRecInt = mbox & 0x1fff;\r
+ //if(gNumRecInt - gNumLastRecInt !=1)\r
+ //if(++gNumLastRecInt > (1<<12))\r
+ //gNumLastRecInt = 0; \r
+ //printk("gNumRecInt=%d,gLastNumInt=%d\n",gNumRecInt,gNumLastRecInt);\r
+ \r
+ if((mbox&MAILBOX_RAM3) == MAILBOX_RAM0)\r
+ { \r
+ //RAM0\r
+ ptr = port->dpram.read_ptr(&port->dpram,SPI_DPRAM_PTR0_BPWRITE_APREAD);\r
+ len = ptr;\r
+ port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START, port->dpram.prx, len);\r
+ port->dpram.rec_len += len; \r
+ printk("%s:ram0:len=%d\n",__FUNCTION__,len); \r
+ //send ack\r
+ //if(++gNumSendAck > (1<<12))\r
+ //gNumSendAck = 0;\r
+ //port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck));\r
+\r
+ //wake up ap to read data\r
+ wake_up_interruptible(&port->dpram.recq);\r
+ \r
+ //printk("%s:r_irq=0x%x,s_ack=0x%x\n",__FUNCTION__,mbox, (MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck));\r
+ }\r
+ else if((mbox&MAILBOX_RAM3) == MAILBOX_RAM2)\r
+ {\r
+ //RAM2\r
+ ptr = port->dpram.read_ptr(&port->dpram,SPI_DPRAM_PTR2_BPWRITE_APREAD);\r
+ len = ptr;\r
+ port->dpram.read_dpram(&port->dpram, SPI_DPRAM_LOG_BPWRITE_START, port->dpram.prx, len);\r
+ port->dpram.rec_len += len; \r
+ printk("%s:ram2:len=%d\n",__FUNCTION__,len); \r
+ //if(++gNumSendAck > (1<<12))\r
+ //gNumSendAck = 0;\r
+ //port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM2 | gNumSendAck));\r
+ \r
+ //wake up ap to read data\r
+ wake_up_interruptible(&port->dpram.recq);\r
+ \r
+ //printk("%s:r_irq=0x%x,s_ack=0x%x\n",__FUNCTION__, mbox, (MAILBOX_APSEND_ACK | MAILBOX_RAM2 | gNumSendAck));\r
+ }\r
\r
\r
-static irqreturn_t spi_dpram_busy_irq(int irq, void *dev_id)\r
+ \r
+}\r
+\r
+static irqreturn_t spi_dpram_irq(int irq, void *dev_id)\r
{\r
struct spi_fpga_port *port = dev_id;\r
\r
* via spi_sync() call.\r
*/\r
\r
- queue_work(port->dpram.spi_dpram_busy_workqueue, &port->dpram.spi_dpram_busy_work);\r
+ queue_work(port->dpram.spi_dpram_irq_workqueue, &port->dpram.spi_dpram_irq_work);\r
\r
return IRQ_HANDLED;\r
}\r
\r
+\r
#if SPI_DPRAM_TEST\r
#define SEL_RAM0 0\r
#define SEL_RAM1 1\r
#define SEL_RAM2 2\r
#define SEL_RAM3 3\r
#define SEL_REG 4\r
-#define SEL_RAM SEL_RAM2\r
-#define DPRAM_TEST_LEN 16 //8bit\r
-unsigned char buf_test_dpram[DPRAM_TEST_LEN];\r
+#define SEL_RAM SEL_REG\r
+\r
void spi_dpram_work_handler(struct work_struct *work)\r
{\r
- int i,j;\r
- int ret;\r
+ int i;\r
struct spi_fpga_port *port =\r
container_of(work, struct spi_fpga_port, dpram.spi_dpram_work);\r
printk("*************test spi_dpram now***************\n");\r
- \r
-#if(SEL_RAM == SEL_RAM0)\r
- //RAM0\r
- for(i=0;i<(SPI_DPRAM_BPWRITE_SIZE/(DPRAM_TEST_LEN>>1));i++)\r
+\r
+ for(i=0;i<SPI_DPRAM_BPWRITE_SIZE;i++)\r
{\r
- port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START+(i*DPRAM_TEST_LEN>>1), port->dpram.prx+i*DPRAM_TEST_LEN, DPRAM_TEST_LEN);\r
+ buf_dpram[2*i] = (0xa000+i)>>8;\r
+ buf_dpram[2*i+1] = (0xa000+i)&0xff;\r
}\r
\r
+#if(SEL_RAM == SEL_RAM0)\r
+ //RAM0\r
+ port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START, port->dpram.prx, SPI_DPRAM_BPWRITE_SIZE<<1);\r
for(i=0;i<SPI_DPRAM_BPWRITE_SIZE;i++)\r
{\r
ret = (*(port->dpram.prx+2*i)<<8) | (*(port->dpram.prx+2*i+1));\r
\r
#elif(SEL_RAM == SEL_RAM1) \r
//RAM1\r
- for(i=0;i<(SPI_DPRAM_APWRITE_SIZE/(DPRAM_TEST_LEN>>1));i++)\r
- { \r
- for(j=(i*(DPRAM_TEST_LEN>>1)); j<((i+1)*(DPRAM_TEST_LEN>>1)); j++)\r
- {\r
- buf_test_dpram[2*(j-(i*(DPRAM_TEST_LEN>>1)))] = (0xa000+j)>>8;\r
- buf_test_dpram[2*(j-(i*(DPRAM_TEST_LEN>>1)))+1] = (0xa000+j)&0xff;\r
- printk("buf_test_dpram[%d]=0x%x\n",j,buf_test_dpram[(j-(i*(DPRAM_TEST_LEN>>1)))]);\r
- }\r
- \r
- port->dpram.write_dpram(&port->dpram, ((DPRAM_TEST_LEN*i)>>1)+SPI_DPRAM_APWRITE_START, buf_test_dpram, sizeof(buf_test_dpram));\r
- mdelay(1);\r
- }\r
- \r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1);\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_START);\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ); //send irq to bp after ap write data to dpram\r
+\r
#elif(SEL_RAM == SEL_RAM2)\r
//RAM2\r
- for(i=0;i<(SPI_DPRAM_LOG_BPWRITE_SIZE/(DPRAM_TEST_LEN>>1));i++)\r
- {\r
- port->dpram.read_dpram(&port->dpram, SPI_DPRAM_LOG_BPWRITE_START+(i*DPRAM_TEST_LEN>>1), port->dpram.prx+i*DPRAM_TEST_LEN, DPRAM_TEST_LEN);\r
- }\r
- \r
+ port->dpram.read_dpram(&port->dpram, SPI_DPRAM_LOG_BPWRITE_START, port->dpram.prx, SPI_DPRAM_LOG_BPWRITE_SIZE<<1); \r
for(i=0;i<SPI_DPRAM_LOG_BPWRITE_SIZE;i++)\r
{\r
ret = (*(port->dpram.prx+2*i)<<8) | (*(port->dpram.prx+2*i+1));\r
if(ret != 0xc000+i)\r
printk("prx[%d]=0x%x ram[%d]=0x%x\n",i,ret&0xffff,i,0xc000+i);\r
}\r
- \r
+\r
#elif(SEL_RAM == SEL_RAM3) \r
//RAM3\r
- for(i=0;i<(SPI_DPRAM_LOG_APWRITE_SIZE/(DPRAM_TEST_LEN>>1));i++)\r
- { \r
- for(j=(i*(DPRAM_TEST_LEN>>1)); j<((i+1)*(DPRAM_TEST_LEN>>1)); j++)\r
- {\r
- buf_test_dpram[2*(j-(i*(DPRAM_TEST_LEN>>1)))] = (0xa000+j)>>8;\r
- buf_test_dpram[2*(j-(i*(DPRAM_TEST_LEN>>1)))+1] = (0xa000+j)&0xff;\r
- printk("buf_test_dpram[%d]=0x%x\n",j,buf_test_dpram[(j-(i*(DPRAM_TEST_LEN>>1)))]);\r
- }\r
- \r
- port->dpram.write_dpram(&port->dpram, ((DPRAM_TEST_LEN*i)>>1)+SPI_DPRAM_LOG_APWRITE_START, buf_test_dpram, sizeof(buf_test_dpram));\r
- mdelay(1);\r
- }\r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_LOG_APWRITE_START, buf_dpram, SPI_DPRAM_LOG_APWRITE_SIZE<<1);\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR3_APWRITE_BPREAD, SPI_DPRAM_LOG_APWRITE_START);\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ); //send irq to bp after ap write data to dpram\r
\r
#elif(SEL_RAM == SEL_REG)\r
-\r
- port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR0_APWRITE_BPREAD, SPI_DPRAM_PTR0_APWRITE_BPREAD);\r
- port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_PTR1_APWRITE_BPREAD);\r
- port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR2_APWRITE_BPREAD, SPI_DPRAM_PTR2_APWRITE_BPREAD);\r
- port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR3_APWRITE_BPREAD, SPI_DPRAM_PTR3_APWRITE_BPREAD);\r
- port->dpram.write_mailbox(&port->dpram, SPI_DPRAM_MAILBOX_APWRITE);\r
-\r
- ret = port->dpram.read_ptr(&port->dpram, SPI_DPRAM_PTR0_BPWRITE_APREAD);\r
- if(ret != SPI_DPRAM_PTR0_BPWRITE_APREAD)\r
- printk("SPI_DPRAM_PTR0_BPWRITE_APREAD(0x%x)=0x%x\n",SPI_DPRAM_PTR0_BPWRITE_APREAD,ret);\r
- \r
- ret = port->dpram.read_ptr(&port->dpram, SPI_DPRAM_PTR1_BPWRITE_APREAD);\r
- if(ret != SPI_DPRAM_PTR1_BPWRITE_APREAD)\r
- printk("SPI_DPRAM_PTR1_BPWRITE_APREAD(0x%x)=0x%x\n",SPI_DPRAM_PTR1_BPWRITE_APREAD,ret);\r
-\r
- ret = port->dpram.read_ptr(&port->dpram, SPI_DPRAM_PTR2_BPWRITE_APREAD);\r
- if(ret != SPI_DPRAM_PTR2_BPWRITE_APREAD)\r
- printk("SPI_DPRAM_PTR2_BPWRITE_APREAD(0x%x)=0x%x\n",SPI_DPRAM_PTR2_BPWRITE_APREAD,ret);\r
-\r
- ret = port->dpram.read_ptr(&port->dpram, SPI_DPRAM_PTR3_BPWRITE_APREAD);\r
- if(ret != SPI_DPRAM_PTR3_BPWRITE_APREAD)\r
- printk("SPI_DPRAM_PTR3_BPWRITE_APREAD(0x%x)=0x%x\n",SPI_DPRAM_PTR3_BPWRITE_APREAD,ret);\r
-\r
- ret = port->dpram.read_mailbox(&port->dpram);\r
- if(ret != SPI_DPRAM_MAILBOX_BPWRITE)\r
- printk("SPI_DPRAM_MAILBOX_BPWRITE(0x%x)=0x%x\n",SPI_DPRAM_MAILBOX_BPWRITE,ret);\r
- \r
-\r
+#if 1\r
+ if(gNumCount++ == 0)\r
+ {\r
+ if(++gNumSendAck > (1<<12))\r
+ gNumSendAck = 0;\r
+ port->dpram.write_ack(&port->dpram, MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck);\r
+ printk("%s:line=%d,s_ack=0x%x\n",__FUNCTION__,__LINE__,MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck);\r
+\r
+ while(port->dpram.apwrite_en != TRUE);\r
+ port->dpram.apwrite_en = FALSE;\r
+ if(++gNumSendInt > (1<<12))\r
+ gNumSendInt = 0;\r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1);\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_SIZE<<1);\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt);\r
+ printk("%s:line=%d,s_irq=0x%x\n",__FUNCTION__,__LINE__,MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt);\r
+\r
+ if(gNumCount > (1<<15))\r
+ gNumCount = 2;\r
+ }\r
#endif\r
\r
+#if 0 \r
+ while(port->dpram.apwrite_en != TRUE);\r
+ port->dpram.apwrite_en == FALSE;\r
+ if(++gNumSendInt > (1<<12))\r
+ gNumSendInt = 0;\r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_LOG_APWRITE_START, buf_dpram, SPI_DPRAM_LOG_APWRITE_SIZE<<1);\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR3_APWRITE_BPREAD, SPI_DPRAM_LOG_APWRITE_SIZE<<1);\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM3 | gNumSendInt);\r
+#endif\r
+#endif\r
\r
}\r
\r
static void spi_testdpram_timer(unsigned long data)\r
{\r
struct spi_fpga_port *port = (struct spi_fpga_port *)data;\r
- port->dpram.dpram_timer.expires = jiffies + msecs_to_jiffies(1000);\r
+ port->dpram.dpram_timer.expires = jiffies + msecs_to_jiffies(500);\r
add_timer(&port->dpram.dpram_timer);\r
//schedule_work(&port->gpio.spi_gpio_work);\r
queue_work(port->dpram.spi_dpram_workqueue, &port->dpram.spi_dpram_work);\r
\r
#endif\r
\r
-\r
-int spi_dpram_handle_irq(struct spi_device *spi)\r
+//really is spi_dpram_handle_ack after dpram's pin is exchanged \r
+int spi_dpram_handle_ack(struct spi_device *spi)\r
{\r
struct spi_fpga_port *port = spi_get_drvdata(spi);\r
- unsigned char mbox = port->dpram.read_mailbox(&port->dpram);\r
- unsigned int len;\r
- DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
- switch(mbox)\r
- {\r
- case MAILBOX_BPWRITE_DATA:\r
- len = port->dpram.read_ptr(&port->dpram,SPI_DPRAM_PTR0_BPWRITE_APREAD);\r
- port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START, port->dpram.prx, len);\r
- port->dpram.rec_len += len;\r
- break;\r
- case MAILBOX_BPREAD_DATA:\r
- port->dpram.apwrite_en = TRUE;\r
- break;\r
- default:\r
- break;\r
- }\r
\r
+ //clear ack interrupt\r
+ port->dpram.read_ack(&port->dpram);\r
+ \r
+ //allow ap to write and wake ap to write data\r
+ port->dpram.apwrite_en = TRUE; \r
+ wake_up_interruptible(&port->dpram.sendq);\r
+#if 0\r
+ //while(port->dpram.apwrite_en != TRUE);\r
+ port->dpram.apwrite_en = FALSE;\r
+ if(++gNumSendInt > (1<<12))\r
+ gNumSendInt = 0;\r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1);\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_SIZE<<1);\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt);\r
+ printk("%s:r_ack=0x%x,s_irq=0x%x\n",__FUNCTION__,ack, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt);\r
+#endif\r
return 0;\r
}\r
\r
{\r
struct spi_fpga_port *port = pFpgaPort;\r
\r
- DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
+ printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
filp->private_data = port;\r
port->dpram.rec_len = 0;\r
port->dpram.send_len = 0;\r
static int dpr_close(struct inode *inode, struct file *filp)\r
{\r
//struct spi_fpga_port *port = pFpgaPort;\r
- DBG("%s:line=%d\n",__FUNCTION__,__LINE__);\r
+ printk("%s:line=%d\n",__FUNCTION__,__LINE__);\r
filp->private_data = NULL;\r
return 0;\r
}\r
{\r
//int ret;\r
struct spi_fpga_port *port = filp->private_data;\r
- DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
+ printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
\r
while(port->dpram.rec_len == 0)\r
{\r
count = port->dpram.rec_len;\r
port->dpram.rec_len = 0;\r
\r
+ //allow bp write ram0 again\r
+ port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM0));\r
+ \r
return count;\r
}\r
\r
static ssize_t dpr_write (struct file *filp, const char __user *buffer, size_t count, loff_t *ppos)\r
{\r
struct spi_fpga_port *port = filp->private_data;\r
- //int ret;\r
- DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); \r
+ int mod,num;\r
+ char i,*p,temp;\r
+ printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); \r
\r
while(port->dpram.apwrite_en == FALSE)\r
{\r
printk("%s:copy_from_user err!\n",__FUNCTION__);\r
return -EFAULT;\r
}\r
-\r
- port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, port->dpram.ptx, count);\r
+ mod = count % 2;\r
+ num = count;\r
+ if(mod)\r
+ {\r
+ *((char *)port->dpram.ptx + count) = 0;\r
+ num = count + 1;\r
+ }\r
+ \r
+ p=port->dpram.ptx;\r
+ \r
+ /*swap data to suitable bp:p[0]<->p[1]*/\r
+ for(i=0;i<(num>>1);i++)\r
+ {\r
+ temp = *(p+(i<<1));\r
+ *(p+(i<<1))= *(p+(i<<1)+1);\r
+ *(p+(i<<1)+1) = temp;\r
+ p=p+2;\r
+ }\r
+ \r
+#if 1\r
+ p=port->dpram.ptx;\r
+ for(i=0;i<num;i++)\r
+ {\r
+ printk("%s:ptx[%d]=0x%x\n",__FUNCTION__,i,*p);\r
+ p++;\r
+ }\r
+#endif\r
+ \r
+ port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, port->dpram.ptx, num);\r
port->dpram.apwrite_en = FALSE; //clear apwrite_en after wirte data to dpram\r
- port->dpram.write_mailbox(&port->dpram, MAILBOX_APSEND_IRQ); //send irq to bp after ap write data to dpram\r
+ port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, count);\r
+ if(++gNumSendInt > (1<<12))\r
+ gNumSendInt = 0;\r
+\r
+ //send irq to bp after ap write data to dpram\r
+ port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ); \r
\r
return count;\r
\r
unsigned int mask = 0;\r
struct spi_fpga_port *port;\r
port = filp->private_data;\r
- DBG("%s:line=%d\n",__FUNCTION__,__LINE__);\r
+ printk("%s:line=%d\n",__FUNCTION__,__LINE__);\r
\r
return mask;\r
}\r
return -ENOMEM;\r
}\r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
- sprintf(b, "spi_dpram_busy_workqueue");\r
- port->dpram.spi_dpram_busy_workqueue = create_freezeable_workqueue(b);\r
- if (!port->dpram.spi_dpram_busy_workqueue) {\r
+ sprintf(b, "spi_dpram_irq_workqueue");\r
+ port->dpram.spi_dpram_irq_workqueue = create_freezeable_workqueue(b);\r
+ if (!port->dpram.spi_dpram_irq_workqueue) {\r
printk("cannot create workqueue\n");\r
return -EBUSY;\r
} \r
- INIT_WORK(&port->dpram.spi_dpram_busy_work, spi_dpram_busy_work_handler);\r
+ INIT_WORK(&port->dpram.spi_dpram_irq_work, spi_dpram_irq_work_handler);\r
\r
#if SPI_DPRAM_TEST\r
sprintf(b, "spi_dpram_workqueue");\r
ret = misc_register(&port->dpram.miscdev);\r
if(ret)\r
{\r
- printk("misc_register err!!!\n");\r
+ printk("%s:misc_register err!!!\n",__FUNCTION__);\r
goto err0;\r
}\r
\r
port->dpram.read_dpram = spi_dpram_read_buf;\r
port->dpram.write_ptr = spi_dpram_write_ptr;\r
port->dpram.read_ptr = spi_dpram_read_ptr;\r
- port->dpram.write_mailbox = spi_dpram_write_mailbox;\r
- port->dpram.read_mailbox = spi_dpram_read_mailbox;\r
+ port->dpram.write_irq = spi_dpram_write_irq;\r
+ port->dpram.read_irq = spi_dpram_read_irq;\r
+ port->dpram.write_ack = spi_dpram_write_ack;\r
+ port->dpram.read_ack = spi_dpram_read_ack;\r
\r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
\r
- ret = gpio_request(SPI_DPRAM_BUSY_PIN, NULL);\r
+ ret = gpio_request(SPI_DPRAM_INT_PIN, NULL);\r
if (ret) {\r
- printk("%s:failed to request fpga busy gpio\n",__FUNCTION__);\r
+ printk("%s:failed to request dpram irq gpio\n",__FUNCTION__);\r
goto err1;\r
}\r
\r
- gpio_pull_updown(SPI_DPRAM_BUSY_PIN,GPIOPullUp);\r
- ret = request_irq(gpio_to_irq(SPI_DPRAM_BUSY_PIN),spi_dpram_busy_irq,IRQF_TRIGGER_RISING,NULL,port);\r
+ rk2818_mux_api_set(GPIOA23_UART2_SEL_NAME,0);\r
+ gpio_pull_updown(SPI_DPRAM_INT_PIN,GPIOPullUp);\r
+ ret = request_irq(gpio_to_irq(SPI_DPRAM_INT_PIN),spi_dpram_irq,IRQF_TRIGGER_FALLING,NULL,port);\r
if(ret)\r
{\r
- printk("unable to request fpga busy_gpio irq\n");\r
+ printk("%s:unable to request dpram irq_gpio irq\n",__FUNCTION__);\r
goto err2;\r
} \r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
return 0;\r
\r
err2:\r
- free_irq(gpio_to_irq(SPI_DPRAM_BUSY_PIN),NULL);\r
+ free_irq(gpio_to_irq(SPI_DPRAM_INT_PIN),NULL);\r
err1: \r
- gpio_free(SPI_DPRAM_BUSY_PIN);\r
+ gpio_free(SPI_DPRAM_INT_PIN);\r
err0:\r
kfree(port->dpram.prx);\r
kfree(port->dpram.ptx);\r
index = port->uart.index;\r
reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index));\r
tx_buf[0] = reg & 0xff;\r
- tx_buf[1] = 0;\r
+ tx_buf[1] = 1;//give fpga 8 clks for reading data\r
rx_buf[0] = 0;\r
rx_buf[1] = 0; \r
- stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx);\r
+ stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx);\r
result = (rx_buf[0] << 8) | rx_buf[1];\r
DBG("%s,SEL_UART reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xff);\r
break;\r
{\r
#if defined(CONFIG_SPI_FPGA_DPRAM)\r
DBG("%s:ICE_INT_TYPE_DPRAM ret=0x%x\n",__FUNCTION__,ret);\r
- spi_dpram_handle_irq(spi);\r
+ spi_dpram_handle_ack(spi);\r
#endif\r
}\r
else\r
}\r
\r
\r
+static int spi_fpga_rst(void)\r
+{\r
+ int ret;\r
+ ret = gpio_request(SPI_FPGA_RST_PIN, NULL);\r
+ if (ret) {\r
+ printk("%s:failed to request fpga rst pin\n",__FUNCTION__);\r
+ return ret;\r
+ }\r
+ rk2818_mux_api_set(GPIOH6_IQ_SEL_NAME,0); \r
+ gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_HIGH);\r
+ gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_LOW);\r
+ mdelay(1);\r
+ gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_HIGH);\r
+\r
+ gpio_direction_input(SPI_FPGA_RST_PIN);\r
+\r
+ return 0;\r
+}\r
+\r
static int __devinit spi_fpga_probe(struct spi_device * spi)\r
{\r
struct spi_fpga_port *port;\r
return -ENOMEM;\r
DBG("port=0x%x\n",(int)port);\r
\r
+ spin_lock_init(&port->work_lock);\r
mutex_init(&port->spi_lock);\r
\r
spi_open_sysclk(GPIO_HIGH);\r
\r
+ spi_fpga_rst();\r
sprintf(b, "fpga_irq_workqueue");\r
port->fpga_irq_workqueue = create_freezeable_workqueue(b);\r
if (!port->fpga_irq_workqueue) {\r
goto err1;\r
}\r
\r
+ rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME,IOMUXB_GPIO2_14_23);\r
gpio_pull_updown(SPI_FPGA_INT_PIN,GPIOPullUp);\r
- ret = request_irq(gpio_to_irq(SPI_FPGA_INT_PIN),spi_fpga_irq,IRQF_TRIGGER_RISING,NULL,port);\r
+ ret = request_irq(gpio_to_irq(SPI_FPGA_INT_PIN),spi_fpga_irq,IRQF_TRIGGER_FALLING,NULL,port);\r
if(ret)\r
{\r
printk("unable to request spi_uart irq\n");\r
spi_gpio_set_pindirection(SPI_GPIO_P2_10, SPI_GPIO_IN); //X-XL input\r
spi_gpio_set_pindirection(SPI_GPIO_P2_11, SPI_GPIO_IN); //X+XR input\r
\r
- spi_gpio_set_pinlevel(SPI_GPIO_P2_12, SPI_GPIO_HIGH); //LCD_RESET output//\r
+ spi_gpio_set_pinlevel(SPI_GPIO_P2_12, SPI_GPIO_LOW); //LCD_RESET output//\r
spi_gpio_set_pindirection(SPI_GPIO_P2_12, SPI_GPIO_OUT);\r
+ spi_gpio_set_pinlevel(SPI_GPIO_P2_12, SPI_GPIO_HIGH);\r
spi_gpio_set_pinlevel(SPI_GPIO_P2_13, SPI_GPIO_HIGH); //USB_PWR_EN output\r
spi_gpio_set_pindirection(SPI_GPIO_P2_13, SPI_GPIO_OUT);\r
spi_gpio_set_pinlevel(SPI_GPIO_P2_14, SPI_GPIO_LOW); //WL_HOST_WAKE_B output\r
t->irq = irq;\r
t->id = ID_SPI_GPIO_IRQ_ENABLE;\r
\r
- spin_lock_irqsave(&port->spi_lock, flags);\r
+ spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
- spin_unlock_irqrestore(&port->spi_lock, flags);\r
+ spin_unlock_irqrestore(&port->work_lock, flags);\r
}\r
\r
static void spi_gpio_irq_disable(unsigned irq)\r
t->irq = irq;\r
t->id = ID_SPI_GPIO_IRQ_DISABLE;\r
\r
- spin_lock_irqsave(&port->spi_lock, flags);\r
+ spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
- spin_unlock_irqrestore(&port->spi_lock, flags);\r
+ spin_unlock_irqrestore(&port->work_lock, flags);\r
\r
\r
}\r
t->id = ID_SPI_GPIO_IRQ_SET_TYPE;\r
t->type = type;\r
\r
- spin_lock_irqsave(&port->spi_lock, flags);\r
+ spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
- spin_unlock_irqrestore(&port->spi_lock, flags);\r
+ spin_unlock_irqrestore(&port->work_lock, flags);\r
return 0;\r
}\r
\r
t->id = ID_SPI_GPIO_IRQ_SET_WAKE;\r
t->state = state;\r
\r
- spin_lock_irqsave(&port->spi_lock, flags);\r
+ spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
- spin_unlock_irqrestore(&port->spi_lock, flags);\r
+ spin_unlock_irqrestore(&port->work_lock, flags);\r
return 0;\r
}\r
\r
#define SPI_UART_TEST 0\r
\r
#define SPI_UART_FIFO_LEN 32\r
-#define SPI_UART_TXRX_BUF 0 //send or recieve several bytes one time\r
+#define SPI_UART_TXRX_BUF 1 //send or recieve several bytes one time\r
\r
static struct tty_driver *spi_uart_tty_driver;\r
/*------------------------ÒÔÏÂÊÇspi2uart±äÁ¿-----------------------*/\r
\r
#define UART_NR 1 /* Number of UARTs this driver can handle */\r
\r
-#define UART_XMIT_SIZE PAGE_SIZE\r
+#define UART_XMIT_SIZE (PAGE_SIZE<<1)\r
#define WAKEUP_CHARS 1024\r
\r
#define circ_empty(circ) ((circ)->head == (circ)->tail)\r
{\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
int index = port->uart.index;\r
- int reg = 0;\r
- unsigned char tx_buf[SPI_UART_TXRX_BUF+2];//uart's tx fifo max lenth + 1\r
- \r
+ int reg = 0, stat = 0;\r
+ int i;\r
+\r
+ for(i=len+2;i>1;i--)\r
+ buf[i] = buf[i-2];\r
reg = ((((reg) | ICE_SEL_UART) & ICE_SEL_WRITE) | ICE_SEL_UART_CH(index));\r
- tx_buf[0] = reg & 0xff;\r
- tx_buf[1] = 0;\r
- memcpy(tx_buf+2, buf, len);\r
- spi_write(port->spi, (const u8 *)&tx_buf, len+2);\r
- DBG("%s,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)tx_buf,len);\r
+ buf[0] = reg & 0xff;\r
+ buf[1] = 0;\r
+\r
+ stat = spi_write(port->spi, buf, len+2);\r
+ if(stat)\r
+ printk("%s:spi_write err!!!\n\n\n",__FUNCTION__); \r
+ DBG("%s:reg=0x%x,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)buf,len);\r
return 0;\r
}\r
\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
int index = port->uart.index;\r
int reg = 0,stat = 0;\r
- unsigned char tx_buf[1],rx_buf[SPI_UART_FIFO_LEN+1];\r
+ unsigned char tx_buf[2],rx_buf[SPI_UART_FIFO_LEN+1];\r
\r
reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index));\r
tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = len;\r
//give fpga 8 clks for reading data\r
- stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, 1, rx_buf, len+1);\r
+ stat = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), rx_buf, len+1); \r
+ if(stat)\r
+ {\r
+ printk("%s:spi_write_then_read is error!,err=%d\n\n",__FUNCTION__,stat);\r
+ return -1;\r
+ }\r
+ \r
memcpy(buf, rx_buf+1, len);\r
- DBG("%s,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)buf,len);\r
+ DBG("%s:reg=0x%x,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)buf,len);\r
return stat;\r
}\r
\r
#endif\r
if (status & UART_MSR_CTS)\r
ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;\r
- DBG("Enter::%s,LINE=%d,ret=0x%x************************\n",__FUNCTION__,__LINE__,ret);\r
+ DBG("%s:LINE=%d,ret=0x%x\n",__FUNCTION__,__LINE__,ret);\r
return ret;\r
}\r
\r
\r
#endif\r
\r
- DBG("Enter::%s,LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr);\r
+ DBG("%s:LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr);\r
spi_out(port, UART_MCR, mcr, SEL_UART);\r
}\r
\r
unsigned int set, unsigned int clear)\r
{\r
unsigned int old;\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
old = uart->mctrl;\r
uart->mctrl = (old & ~clear) | set;\r
if (old != uart->mctrl)\r
spi_out(port, UART_DLM, quot >> 8, SEL_UART);\r
spi_out(port, UART_LCR, cval, SEL_UART);\r
spi_out(port, UART_FCR, fcr, SEL_UART);\r
- DBG("Enter::%s,LINE=%d,baud=%d,uart->ier=0x%x,cval=0x%x,fcr=0x%x,quot=0x%x\n",\r
+ DBG("%s:LINE=%d,baud=%d,uart->ier=0x%x,cval=0x%x,fcr=0x%x,quot=0x%x\n",\r
__FUNCTION__,__LINE__,baud,uart->ier,cval,fcr,quot);\r
spi_uart_write_mctrl(uart, uart->mctrl);\r
}\r
printk("t,");\r
} \r
\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
#endif\r
}\r
\r
//spin_unlock_irqrestore(&uart->write_lock, flags); \r
//printk("p");\r
}\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
}\r
\r
static void spi_uart_stop_rx(struct spi_uart *uart)\r
#if SPI_UART_TXRX_BUF\r
int ret,count,stat = 0,num = 0;\r
unsigned char buf[SPI_UART_FIFO_LEN];\r
- max_count = 512;\r
while (max_count >0 )\r
{\r
ret = spi_in(port, UART_RX, SEL_UART);\r
- count = (ret >> 8) & 0xff; \r
+ count = (ret >> 8) & 0x3f; \r
+ DBG("%s:count=%d\n",__FUNCTION__,count);\r
if(count == 0)\r
break;\r
buf[0] = ret & 0xff;\r
flag = TTY_NORMAL;\r
ch = buf[num++];\r
tty_insert_flip_char(tty, ch, flag);\r
+ //printk("%c,",ch);\r
}\r
- \r
+ //printk("\n");\r
tty_flip_buffer_push(tty); \r
}\r
- printk("r%d\n",1024-max_count);\r
#else \r
//printk("rx:");\r
while (--max_count >0 )\r
break;\r
} \r
//printk("\n");\r
- DBG("Enter::%s,LINE=%d,rx_count=%d********\n",__FUNCTION__,__LINE__,(1024-max_count));\r
- printk("r%d\n",1024-max_count);\r
+ DBG("%s:LINE=%d,rx_count=%d\n",__FUNCTION__,__LINE__,(1024-max_count));\r
tty_flip_buffer_push(tty);\r
\r
#endif\r
+ printk("r%d\n",1024-max_count);\r
\r
}\r
\r
spi_out(port, UART_TX, uart->x_char, SEL_UART);\r
uart->icount.tx++;\r
uart->x_char = 0;\r
- printk("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ printk("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
return;\r
}\r
if (circ_empty(xmit) || uart->tty->stopped || uart->tty->hw_stopped) {\r
spi_uart_stop_tx(uart);\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
//printk("circ_empty()\n");\r
return;\r
}\r
\r
#if SPI_UART_TXRX_BUF\r
//send several bytes one time\r
- count = 0;\r
- while(count < SPI_UART_FIFO_LEN)\r
+ count = SPI_UART_FIFO_LEN;\r
+ while(count > 0)\r
{\r
- buf[count] = xmit->buf[xmit->tail];\r
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
- uart->icount.tx++;\r
- count++;\r
if (circ_empty(xmit))\r
break;\r
+ buf[SPI_UART_FIFO_LEN - count] = xmit->buf[xmit->tail];\r
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
+ uart->icount.tx++;\r
+ --count;\r
}\r
- spi_uart_write_buf(uart,buf,count);\r
+ if(SPI_UART_FIFO_LEN - count > 0)\r
+ spi_uart_write_buf(uart,buf,SPI_UART_FIFO_LEN - count);\r
#else\r
//send one byte one time\r
- count = SPI_UART_FIFO_LEN;//\r
+ count = SPI_UART_FIFO_LEN;\r
while(count > 0)\r
{\r
spi_out(port, UART_TX, xmit->buf[xmit->tail], SEL_UART);\r
}\r
#endif\r
//printk("\n");\r
- DBG("Enter::%s,LINE=%d,tx_count=%d\n",__FUNCTION__,__LINE__,(32-count));\r
+ DBG("%s:LINE=%d,tx_count=%d\n",__FUNCTION__,__LINE__,(SPI_UART_FIFO_LEN-count));\r
if (circ_chars_pending(xmit) < WAKEUP_CHARS)\r
{ \r
tty_wakeup(uart->tty);\r
- printk("k,");\r
+ //printk("k,");\r
}\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
if (circ_empty(xmit))\r
{\r
DBG("circ_empty(xmit)\n");\r
spi_uart_stop_tx(uart);\r
- printk("e,");\r
+ //printk("e,");\r
}\r
\r
- printk("t%d\n",32-count);\r
+ printk("t%d\n",SPI_UART_FIFO_LEN-count);\r
\r
DBG("uart->tty->hw_stopped = %d\n",uart->tty->hw_stopped);\r
}\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
\r
status = spi_in(port, UART_MSR, SEL_UART);//\r
- DBG("Enter::%s,LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status);\r
+ DBG("%s:LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status);\r
if ((status & UART_MSR_ANY_DELTA) == 0)\r
return;\r
\r
if (cts) {\r
uart->tty->hw_stopped = 0;\r
spi_uart_start_tx(uart);\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
tty_wakeup(uart->tty);\r
}\r
} else {\r
if (!cts) {\r
uart->tty->hw_stopped = 1;\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
spi_uart_stop_tx(uart);\r
}\r
}\r
}\r
}\r
- DBG("Enter::%s,LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status);\r
+ DBG("%s:LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status);\r
}\r
#endif\r
\r
\r
#if SPI_UART_TEST\r
-#define UART_TEST_LEN 16 //8bit\r
-unsigned char buf_test_uart[UART_TEST_LEN];\r
+#define UART_TEST_LEN 32 //8bit\r
+unsigned char buf_test_uart[UART_TEST_LEN+2];\r
\r
void spi_uart_test_init(struct spi_fpga_port *port)\r
{\r
unsigned char mcr = 0;\r
int ret;\r
\r
- DBG("Enter::%s,LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr);\r
+ DBG("%s:LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr);\r
spi_out(port, UART_MCR, mcr, SEL_UART);\r
baud = 1500000;\r
cval = UART_LCR_WLEN8;\r
spi_out(port, UART_LCR, cval | UART_LCR_DLAB, SEL_UART);\r
spi_out(port, UART_DLL, quot & 0xff, SEL_UART); \r
ret = spi_in(port, UART_DLL, SEL_UART)&0xff;\r
- printk("%s:quot=0x%x,UART_DLL=0x%x\n",__FUNCTION__,quot,ret);\r
+ if(ret != quot)\r
+ {\r
+ #if SPI_FPGA_TEST_DEBUG\r
+ spi_test_wrong_handle();\r
+ #endif\r
+ printk("%s:quot=0x%x,UART_DLL=0x%x\n",__FUNCTION__,quot,ret);\r
+ }\r
spi_out(port, UART_DLM, quot >> 8, SEL_UART); \r
spi_out(port, UART_LCR, cval, SEL_UART);\r
spi_out(port, UART_FCR, fcr, SEL_UART);\r
for(i=0;i<UART_TEST_LEN;i++)\r
buf_test_uart[i] = '0'+i; \r
count = UART_TEST_LEN;\r
+\r
#if SPI_UART_TXRX_BUF\r
spi_uart_write_buf(&port->uart, buf_test_uart, count);\r
+ mdelay(5);\r
+ spi_uart_read_buf(&port->uart, buf_test_uart, count);\r
+ for(i=0;i<UART_TEST_LEN;i++)\r
+ {\r
+ if(buf_test_uart[i] != '0'+i)\r
+ {\r
+ #if SPI_FPGA_TEST_DEBUG\r
+ spi_test_wrong_handle();\r
+ #endif\r
+ printk("err:%s:buf_t[%d]=0x%x,buf_r[%d]=0x%x\n",__FUNCTION__,i,'0'+i,i,buf_test_uart[i]);\r
+ }\r
+ }\r
#else\r
while(count > 0)\r
{\r
spi_out(port, UART_TX, buf_test_uart[UART_TEST_LEN-count], SEL_UART);\r
--count;\r
}\r
+ printk("%s,line=%d\n",__FUNCTION__,__LINE__);\r
#endif\r
\r
}\r
static void spi_testuart_timer(unsigned long data)\r
{\r
struct spi_fpga_port *port = (struct spi_fpga_port *)data;\r
- port->uart.uart_timer.expires = jiffies + msecs_to_jiffies(1000);\r
+ port->uart.uart_timer.expires = jiffies + msecs_to_jiffies(300);\r
add_timer(&port->uart.uart_timer);\r
//schedule_work(&port->gpio.spi_gpio_work);\r
queue_work(port->uart.spi_uart_workqueue, &port->uart.spi_uart_work);\r
\r
#endif\r
\r
-\r
-\r
-\r
/*\r
* This handles the interrupt from one port.\r
*/\r
\r
if (unlikely(uart->in_spi_uart_irq == current))\r
return;\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
\r
/*\r
* In a few places spi_uart_handle_irq() is called directly instead of\r
*/\r
\r
uart_iir = spi_in(port, UART_IIR, SEL_UART);// \r
+ DBG("%s:iir=0x%x\n",__FUNCTION__,uart_iir); \r
if (uart_iir & UART_IIR_NO_INT)\r
return;\r
- \r
- DBG("iir=0x%x\n",uart_iir);\r
\r
uart->in_spi_uart_irq = current;\r
lsr = spi_in(port, UART_LSR, SEL_UART);//\r
- DBG("lsr=0x%x\n",lsr);\r
+ DBG("%s:lsr=0x%x\n",__FUNCTION__,lsr);\r
\r
if (lsr & UART_LSR_DR)\r
//if (((uart_iir & UART_IIR_RDI) | (uart_iir & UART_IIR_RLSI)) && (lsr & UART_LSR_DR))\r
{\r
- DBG("Enter::%s,LINE=%d,lsr & UART_LSR_DR************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d,start recieve data!\n",__FUNCTION__,__LINE__);\r
spi_uart_receive_chars(uart, &lsr); \r
}\r
\r
if (lsr & UART_LSR_THRE)\r
//if ((uart_iir & UART_IIR_THRI)&&(lsr & UART_LSR_THRE))\r
{\r
- DBG("Enter::%s,LINE=%d,ICE_STATUS_TXF == 0************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d,start send data!\n",__FUNCTION__,__LINE__);\r
spi_uart_transmit_chars(uart);\r
}\r
\r
uart->in_spi_uart_irq = NULL;\r
\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
\r
}\r
\r
unsigned long page;\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
/*\r
* Set the TTY IO error marker - we will only clear this\r
* once we have successfully opened the port.\r
uart->tty->hw_stopped = 1;\r
\r
clear_bit(TTY_IO_ERROR, &uart->tty->flags);\r
- DBG("Enter::%s,LINE=%d,uart->ier=0x%x\n",__FUNCTION__,__LINE__,uart->ier);\r
+ DBG("%s:LINE=%d,uart->ier=0x%x\n",__FUNCTION__,__LINE__,uart->ier);\r
/* Kick the IRQ handler once while we're still holding the host lock */\r
//spi_uart_handle_irq(port->spi);\r
//mutex_unlock(&port->spi_lock);\r
static void spi_uart_shutdown(struct spi_uart *uart)\r
{\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
+\r
//mutex_lock(&port->spi_lock);\r
+#if 1\r
spi_uart_stop_rx(uart);\r
\r
/* TODO: wait here for TX FIFO to drain */\r
UART_FCR_CLEAR_RCVR |\r
UART_FCR_CLEAR_XMIT, SEL_UART);\r
spi_out(port, UART_FCR, 0, SEL_UART);\r
-\r
+#endif\r
//mutex_unlock(&port->spi_lock);\r
\r
//skip:\r
uart = spi_uart_port_get(tty->index);\r
if (!uart)\r
{\r
- DBG("Enter::%s,LINE=%d,!port\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d,!port\n",__FUNCTION__,__LINE__);\r
return -ENODEV;\r
}\r
- DBG("Enter::%s,LINE=%d,tty->index=%d\n",__FUNCTION__,__LINE__,tty->index);\r
+ DBG("%s:LINE=%d,tty->index=%d\n",__FUNCTION__,__LINE__,tty->index);\r
mutex_lock(&uart->open_lock);\r
\r
/*\r
if (tty->driver_data && tty->driver_data != uart) {\r
mutex_unlock(&uart->open_lock);\r
spi_uart_port_put(uart);\r
- DBG("Enter::%s,LINE=%d,!= uart\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d,!= uart\n",__FUNCTION__,__LINE__);\r
return -EBUSY;\r
}\r
\r
uart->tty = NULL;\r
mutex_unlock(&uart->open_lock);\r
spi_uart_port_put(uart);\r
- DBG("Enter::%s,LINE=%d,ret=%d\n",__FUNCTION__,__LINE__,ret);\r
+ DBG("%s:LINE=%d,ret=%d\n",__FUNCTION__,__LINE__,ret);\r
return ret;\r
}\r
}\r
uart->opened++;\r
- DBG("Enter::%s,uart->opened++=%d\n",__FUNCTION__,uart->opened);\r
+ DBG("%s:uart->opened++=%d\n",__FUNCTION__,uart->opened);\r
mutex_unlock(&uart->open_lock);\r
return 0;\r
}\r
static void spi_uart_close(struct tty_struct *tty, struct file * filp)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
- printk("Enter::%s,LINE=%d,tty->hw_stopped=%d\n",__FUNCTION__,__LINE__,tty->hw_stopped);\r
+ printk("%s:LINE=%d,tty->hw_stopped=%d\n",__FUNCTION__,__LINE__,tty->hw_stopped);\r
if (!uart)\r
return;\r
\r
}\r
\r
if (--uart->opened == 0) {\r
- DBG("Enter::%s,opened=%d\n",__FUNCTION__,uart->opened);\r
+ DBG("%s:opened=%d\n",__FUNCTION__,uart->opened);\r
tty->closing = 1;\r
spi_uart_shutdown(uart);\r
tty_ldisc_flush(tty);\r
#if 1\r
if ( !(uart->ier & UART_IER_THRI)) {\r
//mutex_lock(&port->spi_lock);\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
/*Note:ICE65L08 output a 'Transmitter holding register interrupt' after 1us*/\r
- //printk("s,");\r
+ printk("s,");\r
spi_uart_start_tx(uart);\r
- spi_uart_handle_irq(port->spi);\r
+ // spi_uart_handle_irq(port->spi);\r
//mutex_unlock(&port->spi_lock); \r
} \r
#endif \r
static int spi_uart_write_room(struct tty_struct *tty)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
- DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
return uart ? circ_chars_free(&uart->xmit) : 0;\r
}\r
\r
static int spi_uart_chars_in_buffer(struct tty_struct *tty)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
- printk("Enter::%s,LINE=%d,circ=%ld****\n",__FUNCTION__,__LINE__,circ_chars_pending(&uart->xmit)); \r
+ printk("%s:LINE=%d,circ=%ld\n",__FUNCTION__,__LINE__,circ_chars_pending(&uart->xmit)); \r
return uart ? circ_chars_pending(&uart->xmit) : 0;\r
}\r
\r
{\r
struct spi_uart *uart = tty->driver_data;\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
- printk("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ printk("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
uart->x_char = ch;\r
if (ch && !(uart->ier & UART_IER_THRI)) {\r
//mutex_lock(&port->spi_lock);\r
spi_uart_start_tx(uart);\r
- printk("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ printk("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
spi_uart_handle_irq(port->spi);\r
//mutex_unlock(&port->spi_lock); \r
}\r
{\r
struct spi_uart *uart = tty->driver_data;\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
- printk("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ printk("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
if (!I_IXOFF(tty) && !(tty->termios->c_cflag & CRTSCTS))\r
return;\r
- printk("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ printk("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
//mutex_lock(&port->spi_lock);\r
if (I_IXOFF(tty)) {\r
uart->x_char = STOP_CHAR(tty);\r
spi_uart_start_tx(uart);\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
}\r
\r
if (tty->termios->c_cflag & CRTSCTS)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
- printk("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ printk("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
if (!I_IXOFF(tty) && !(tty->termios->c_cflag & CRTSCTS))\r
return;\r
//mutex_lock(&port->spi_lock);\r
} else {\r
uart->x_char = START_CHAR(tty);\r
spi_uart_start_tx(uart);\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
}\r
}\r
\r
static void spi_uart_set_termios(struct tty_struct *tty, struct ktermios *old_termios)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
+ //struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
unsigned int cflag = tty->termios->c_cflag;\r
unsigned int mask = TIOCM_DTR;\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
\r
#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))\r
\r
\r
/* Handle transition to B0 status */\r
if ((old_termios->c_cflag & CBAUD) && !(cflag & CBAUD)){\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
spi_uart_clear_mctrl(uart, TIOCM_RTS | TIOCM_DTR);\r
//spi_uart_clear_mctrl(uart, TIOCM_RTS);\r
}\r
\r
/* Handle transition away from B0 status */\r
if (!(old_termios->c_cflag & CBAUD) && (cflag & CBAUD)) {\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
if (!(cflag & CRTSCTS) || !test_bit(TTY_THROTTLED, &tty->flags))\r
mask |= TIOCM_RTS;\r
spi_uart_set_mctrl(uart, mask);\r
\r
/* Handle turning off CRTSCTS */\r
if ((old_termios->c_cflag & CRTSCTS) && !(cflag & CRTSCTS)) {\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
tty->hw_stopped = 0;\r
spi_uart_start_tx(uart);\r
- DBG("Enter::%s,UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
+ DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier);\r
}\r
\r
/* Handle turning on CRTSCTS */\r
if (!(old_termios->c_cflag & CRTSCTS) && (cflag & CRTSCTS)) {\r
- DBG("Enter::%s,LINE=%d,status=0x%x,Handle turning on CRTSCTS*****************\n",__FUNCTION__,__LINE__,spi_uart_get_mctrl(uart));\r
//spi_uart_set_mctrl(uart, TIOCM_RTS);\r
if (!(spi_uart_get_mctrl(uart) & TIOCM_CTS)) {\r
- DBG("Enter::%s,LINE=%d,tty->hw_stopped = 1********\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d,tty->hw_stopped = 1\n",__FUNCTION__,__LINE__);\r
tty->hw_stopped = 1;\r
spi_uart_stop_tx(uart);\r
}\r
{\r
struct spi_uart *uart = tty->driver_data;\r
struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); \r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
//mutex_lock(&port->spi_lock);\r
if (break_state == -1)\r
uart->lcr |= UART_LCR_SBC;\r
static int spi_uart_tiocmget(struct tty_struct *tty, struct file *file)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
+ //struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
int result;\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
//mutex_lock(&port->spi_lock);\r
result = uart->mctrl | spi_uart_get_mctrl(uart);\r
//mutex_unlock(&port->spi_lock);\r
unsigned int set, unsigned int clear)\r
{\r
struct spi_uart *uart = tty->driver_data;\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ //struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart);\r
+ DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__);\r
//mutex_lock(&port->spi_lock);\r
spi_uart_update_mctrl(uart, set, clear);\r
//mutex_unlock(&port->spi_lock);\r
{\r
int i, len = 0;\r
off_t begin = 0;\r
- DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
+ DBG("%s:LINE=%d************************\n",__FUNCTION__,__LINE__);\r
len += sprintf(page, "serinfo:1.0 driver%s%s revision:%s\n",\r
"", "", "");\r
for (i = 0; i < UART_NR && len < PAGE_SIZE - 96; i++) {\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff