Teach EmitLiveInCopies to omit copies for unused virtual registers,

and to clean up unused incoming physregs from the live-in list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index 631c43c6b32116951d1a9c361633dd8ce5bd3c65..64a3753ab07c04a2eec4354c2f0b1ab8b1d88cda 100644 (file)
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -182,21 +182,32 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
                                       const TargetRegisterInfo &TRI,
                                       const TargetInstrInfo &TII) {
   // Emit the copies into the top of the block.
-  for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
-         E = livein_end(); LI != E; ++LI)
-    if (LI->second) {
-      const TargetRegisterClass *RC = getRegClass(LI->second);
-      bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
-                                      LI->second, LI->first, RC, RC,
-                                      DebugLoc());
-      assert(Emitted && "Unable to issue a live-in copy instruction!\n");
-      (void) Emitted;
+  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
+    if (LiveIns[i].second) {
+      if (use_empty(LiveIns[i].second)) {
+        // The livein has no uses. Drop it.
+        //
+        // It would be preferable to have isel avoid creating live-in
+        // records for unused arguments in the first place, but it's
+        // complicated by the debug info code for arguments.
+        LiveIns.erase(LiveIns.begin() + i);
+        --i; --e;
+      } else {
+        // Emit a copy.
+        const TargetRegisterClass *RC = getRegClass(LiveIns[i].second);
+        bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
+                                        LiveIns[i].second, LiveIns[i].first,
+                                        RC, RC, DebugLoc());
+        assert(Emitted && "Unable to issue a live-in copy instruction!\n");
+        (void) Emitted;
+
+        // Add the register to the entry block live-in set.
+        EntryMBB->addLiveIn(LiveIns[i].first);
+      }
+    } else {
+      // Add the register to the entry block live-in set.
+      EntryMBB->addLiveIn(LiveIns[i].first);
     }
-
-  // Add function live-ins to entry block live-in set.
-  for (MachineRegisterInfo::livein_iterator I = livein_begin(),
-         E = livein_end(); I != E; ++I)
-    EntryMBB->addLiveIn(I->first);
 }
 
 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {

diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll
index 76332cc290ccf48664937fee7b06c8a40f49f2c7..688b7bc312c7b10b62b7f976867a82edebadc448 100644 (file)
--- a/test/CodeGen/ARM/long_shift.ll
+++ b/test/CodeGen/ARM/long_shift.ll
@@ -23,10 +23,10 @@ define i32 @f1(i64 %x, i64 %y) {
 define i32 @f2(i64 %x, i64 %y) {
 ; CHECK: f2
 ; CHECK:      mov     r0, r0, lsr r2
-; CHECK-NEXT: rsb     r12, r2, #32
+; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: sub     r2, r2, #32
 ; CHECK-NEXT: cmp     r2, #0
-; CHECK-NEXT: orr     r0, r0, r1, lsl r12
+; CHECK-NEXT: orr     r0, r0, r1, lsl r3
 ; CHECK-NEXT: movge   r0, r1, asr r2
        %a = ashr i64 %x, %y
        %b = trunc i64 %a to i32
@@ -36,10 +36,10 @@ define i32 @f2(i64 %x, i64 %y) {
 define i32 @f3(i64 %x, i64 %y) {
 ; CHECK: f3
 ; CHECK:      mov     r0, r0, lsr r2
-; CHECK-NEXT: rsb     r12, r2, #32
+; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: sub     r2, r2, #32
 ; CHECK-NEXT: cmp     r2, #0
-; CHECK-NEXT: orr     r0, r0, r1, lsl r12
+; CHECK-NEXT: orr     r0, r0, r1, lsl r3
 ; CHECK-NEXT: movge   r0, r1, lsr r2
        %a = lshr i64 %x, %y
        %b = trunc i64 %a to i32

diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index b969ecb4142003f460da29f00577c91c61ae8f88..206cdff1ba7d01a05a7eaeddab0719e49a1e0291 100644 (file)
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -63,10 +63,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
        ret <8 x i16> %tmp
 ; X64: t4:
 ; X64:         pextrw  $7, %xmm0, %eax
-; X64:         pshufhw $100, %xmm0, %xmm2
-; X64:         pinsrw  $1, %eax, %xmm2
+; X64:         pshufhw $100, %xmm0, %xmm1
+; X64:         pinsrw  $1, %eax, %xmm1
 ; X64:         pextrw  $1, %xmm0, %eax
-; X64:         movdqa  %xmm2, %xmm0
+; X64:         movdqa  %xmm1, %xmm0
 ; X64:         pinsrw  $4, %eax, %xmm0
 ; X64:         ret
 }