[ARM] tegra: clock: Don't use PLL lock bits

The PLL lock bits are not reliable, use per-PLL timeouts instead.

Change-Id: I2749e0d8bcfb0b60dbbcf6378b38307f77ff8d4d
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 096922c4d6645a253510bda085163b8c461909ea..2dffa8aff4352fedf59c5403e54224dd4eb8061f 100644 (file)
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -53,7 +53,6 @@ struct dvfs_process_id_table {
        struct dvfs_table *table;
 };
 
-
 struct dvfs {
        struct regulator *reg;
        struct dvfs_table *table;
@@ -128,6 +127,7 @@ struct clk {
        unsigned long                   vco_min;
        unsigned long                   vco_max;
        const struct clk_pll_table      *pll_table;
+       int                             pll_lock_delay;
 
        /* DIV */
        u32                             div;

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 5b75cb3f5146503674e6217896a77059566f3bbd..125881e9fe2245bad30244c8f931d51486c7ae9f 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -80,7 +80,6 @@
 #define PLL_BASE_ENABLE                        (1<<30)
 #define PLL_BASE_REF_ENABLE            (1<<29)
 #define PLL_BASE_OVERRIDE              (1<<28)
-#define PLL_BASE_LOCK                  (1<<27)
 #define PLL_BASE_DIVP_MASK             (0x7<<20)
 #define PLL_BASE_DIVP_SHIFT            20
 #define PLL_BASE_DIVN_MASK             (0x3FF<<8)
@@ -95,7 +94,6 @@
 #define PLL_OUT_RESET_DISABLE          (1<<0)
 
 #define PLL_MISC(c)                    (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-#define PLL_MISC_LOCK_ENABLE(c)                (((c)->flags & PLLU) ? (1<<22) : (1<<18))
 
 #define PLL_MISC_DCCON_SHIFT           20
 #define PLL_MISC_CPCON_SHIFT           8
@@ -571,17 +569,7 @@ static struct clk_ops tegra_blink_clk_ops = {
 /* PLL Functions */
 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
 {
-       ktime_t before;
-
-       before = ktime_get();
-
-       while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
-               if (ktime_us_delta(ktime_get(), before) > 5000) {
-                       pr_err("Timed out waiting for lock bit on pll %s",
-                               c->name);
-                       return -1;
-               }
-       }
+       udelay(c->pll_lock_delay);
 
        return 0;
 }
@@ -619,10 +607,6 @@ static int tegra2_pll_clk_enable(struct clk *c)
        val |= PLL_BASE_ENABLE;
        clk_writel(val, c->reg + PLL_BASE);
 
-       val = clk_readl(c->reg + PLL_MISC(c));
-       val |= PLL_MISC_LOCK_ENABLE(c);
-       clk_writel(val, c->reg + PLL_MISC(c));
-
        tegra2_pll_clk_wait_for_lock(c);
 
        return 0;
@@ -1177,6 +1161,7 @@ static struct clk tegra_pll_s = {
        .vco_max   = 26000000,
        .pll_table = tegra_pll_s_table,
        .max_rate  = 26000000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk_mux_sel tegra_clk_m_sel[] = {
@@ -1213,6 +1198,7 @@ static struct clk tegra_pll_c = {
        .vco_max   = 1400000000,
        .pll_table = tegra_pll_c_table,
        .max_rate  = 600000000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk tegra_pll_c_out1 = {
@@ -1251,6 +1237,7 @@ static struct clk tegra_pll_m = {
        .vco_max   = 1200000000,
        .pll_table = tegra_pll_m_table,
        .max_rate  = 800000000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk tegra_pll_m_out1 = {
@@ -1289,6 +1276,7 @@ static struct clk tegra_pll_p = {
        .vco_max   = 1400000000,
        .pll_table = tegra_pll_p_table,
        .max_rate  = 432000000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk tegra_pll_p_out1 = {
@@ -1354,6 +1342,7 @@ static struct clk tegra_pll_a = {
        .vco_max   = 1400000000,
        .pll_table = tegra_pll_a_table,
        .max_rate  = 56448000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk tegra_pll_a_out0 = {
@@ -1399,6 +1388,7 @@ static struct clk tegra_pll_d = {
        .vco_max   = 1000000000,
        .pll_table = tegra_pll_d_table,
        .max_rate  = 1000000000,
+       .pll_lock_delay = 1000,
 };
 
 static struct clk tegra_pll_d_out0 = {
@@ -1431,6 +1421,7 @@ static struct clk tegra_pll_u = {
        .vco_max   = 960000000,
        .pll_table = tegra_pll_u_table,
        .max_rate  = 480000000,
+       .pll_lock_delay = 1000,
 };
 
 static struct clk_pll_table tegra_pll_x_table[] = {
@@ -1493,6 +1484,7 @@ static struct clk tegra_pll_x = {
        .vco_max   = 1200000000,
        .pll_table = tegra_pll_x_table,
        .max_rate  = 1000000000,
+       .pll_lock_delay = 300,
 };
 
 static struct clk tegra_clk_d = {
@@ -1960,7 +1952,6 @@ static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
 void tegra_clk_suspend(void)
 {
        unsigned long off, i;
-       u32 pllx_misc;
        u32 *ctx = clk_rst_suspend;
 
        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
@@ -2001,10 +1992,6 @@ void tegra_clk_suspend(void)
 
        *ctx++ = clk_readl(MISC_CLK_ENB);
        *ctx++ = clk_readl(CLK_MASK_ARM);
-
-       pllx_misc = clk_readl(tegra_pll_x.reg + PLL_MISC(&tegra_pll_x));
-       pllx_misc &= ~PLL_MISC_LOCK_ENABLE(&tegra_pll_x);
-       clk_writel(pllx_misc, tegra_pll_x.reg + PLL_MISC(&tegra_pll_x));
 }
 
 void tegra_clk_resume(void)