Stop adding bogus operands to variable shifts on X86. These instructions

only take one operand.  The other comes implicitly in through CL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22887 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 7bf481faf8fd8d9e2ad43c4e13b5e07675943107..e78a9df62c881d0728533bb5ee15d3fd539be577 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -3223,7 +3223,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     case MVT::i32: Opc = X86::SHL32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
   case ISD::SRL:
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -3253,7 +3253,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     case MVT::i32: Opc = X86::SHR32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
   case ISD::SRA:
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {