R600/SI: Add support for v2f32 stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186614 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index e2fd369f86996ca874ad95de1af88979e0c73af7..666e1580918ee2e94ff9fe37053e851cd8299aea 100644 (file)
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -57,6 +57,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::STORE, MVT::f32, Promote);
   AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
 
+  setOperationAction(ISD::STORE, MVT::v2f32, Promote);
+  AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
+
   setOperationAction(ISD::STORE, MVT::v4f32, Promote);
   AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
 

diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 95e86d794cacde209171a925edbfacd507ca9bd1..76b73de9fb47418fd2ca282f103f5002a03b2ceb 100644 (file)
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1484,6 +1484,9 @@ def : BitConvert <i64, f64, VReg_64>;
 
 def : BitConvert <f64, i64, VReg_64>;
 
+def : BitConvert <v2f32, v2i32, VReg_64>;
+def : BitConvert <v2i32, v2f32, VReg_64>;
+
 /********** =================== **********/
 /********** Src & Dst modifiers **********/
 /********** =================== **********/

diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index f8c6f8414c030ebf273bfa2aa2a00d73b14790c3..d233c73b805891531cda00b207aee2cce025b1f7 100644 (file)
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -15,6 +15,24 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
   ret void
 }
 
+; vec2 floating-point stores
+; EG-CHECK: @store_v2f32
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
+; EG-CHECK-NEXT: RAT_WRITE_CACHELESS_32_eg
+; CM-CHECK: @store_v2f32
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; CM-CHECK-NEXT: EXPORT_RAT_INST_STORE_DWORD
+; SI-CHECK: @store_v2f32
+; SI-CHECK: BUFFER_STORE_DWORDX2
+
+define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
+entry:
+  %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
+  %1 = insertelement <2 x float> %0, float %b, i32 0
+  store <2 x float> %1, <2 x float> addrspace(1)* %out
+  ret void
+}
+
 ; The stores in this function are combined by the optimizer to create a
 ; 64-bit store with 32-bit alignment.  This is legal for SI and the legalizer
 ; should not try to split the 64-bit store back into 2 32-bit stores.