0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol}, //update\r
- //576p-50hz\r
+ //1080p-60hz\r
+ {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+ 0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+ //576p-50hz\r
{0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+ \r
+ //1080p-50hz\r
+ {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+ 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+ 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+ 0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
+ ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
};\r
//#endif\r
int anx7150_mass_read_need_delay = 0;\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
+ hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
find_resolution = 1;\r
}\r
break;\r
+ case HDMI_1920x1080p_50Hz:\r
+ if(ANX7150_edid_result.supported_1080p_50Hz){\r
+ resolution_real = HDMI_1920x1080p_50Hz;\r
+ find_resolution = 1;\r
+ }\r
+ break;\r
default:\r
break;\r
}\r
resolution_real = HDMI_1280x720p_60Hz;\r
else if(ANX7150_edid_result.supported_576p_50Hz)\r
resolution_real = HDMI_720x576p_50Hz;\r
+ else if(ANX7150_edid_result.supported_1080p_50Hz)\r
+ resolution_real = HDMI_1920x1080p_50Hz;\r
else\r
resolution_real = HDMI_1280x720p_50Hz;\r
}\r
static void ANX7150_Get_Video_Timing(void)\r
{\r
u8 i;\r
+ \r
//#ifdef ITU656\r
for (i = 0; i < 18; i++)\r
{\r
rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
c |= (ANX7150_VID_CTRL_IN_EN);\r
rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
+ msleep(200);\r
//D("Video configure OK!\n");\r
rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
if (!(c & ANX7150_VID_STATUS_VID_STABLE))\r
{\r
//disable super audio output\r
hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
+ c = 0x00;\r
rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
}\r
\r
rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
c = 0x00;\r
rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xf8) | FREQ_MCLK;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
\r
// set the relation of MCLK and Fs xy 070117\r
+ rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+ c = (c & 0xf8) | FREQ_MCLK;\r
+ rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
\r
//Enable control of ACR\r
case HDMI_720x576p_50Hz:\r
g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
break;\r
+ case HDMI_1920x1080p_50Hz:\r
+ g_video_format = ANX7150_V1920x1080p_50Hz;\r
+ break;\r
default:\r
g_video_format = ANX7150_V1280x720p_50Hz;\r
break;\r
#define V_VD3 576
#define V_FP3 5
+/* 1080p@50Hz Timing */
+#define OUT_CLK4 148500000
+#define H_PW4 44
+#define H_BP4 148
+#define H_VD4 1920
+#define H_FP4 528
+#define V_PW4 5
+#define V_BP4 35
+#define V_VD4 1080
+#define V_FP4 5
+
+
extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable );
static int anx7150_init(void)
{
struct rk29fb_screen *screen2 = screen + 1;
struct rk29fb_screen *screen3 = screen + 2;
+ struct rk29fb_screen *screen4 = screen + 3;
/* ****************** 720p@60Hz ******************* */
/* screen type & face */
/* Operation function*/
screen3->init = anx7150_init;
screen3->standby = anx7150_standby;
+ /* ****************** 1080p@50Hz ******************* */
+ /* screen type & face */
+ screen4->type = OUT_TYPE;
+ screen4->face = OUT_FACE;
+
+ /* Screen size */
+ screen4->x_res = H_VD4;
+ screen4->y_res = V_VD4;
+
+ /* Timing */
+ screen4->pixclock = OUT_CLK4;
+ screen4->left_margin = H_BP4;
+ screen4->right_margin = H_FP4;
+ screen4->hsync_len = H_PW4;
+ screen4->upper_margin = V_BP4;
+ screen4->lower_margin = V_FP4;
+ screen4->vsync_len = V_PW4;
+
+ /* Pin polarity */
+ screen4->pin_hsync = 0;
+ screen4->pin_vsync = 0;
+ screen4->pin_den = 0;
+ screen4->pin_dclk = DCLK_POL;
+
+ /* Swap rule */
+ screen4->swap_rb = SWAP_RB;
+ screen4->swap_rg = 0;
+ screen4->swap_gb = 0;
+ screen4->swap_delta = 0;
+ screen4->swap_dumy = 0;
+
+ /* Operation function*/
+ screen4->init = anx7150_init;
+ screen4->standby = anx7150_standby;
}
int hdmi_switch_fb(int resolution, int type)
{
int rc = 0;
- struct rk29fb_screen hdmi_info[3];
+ struct rk29fb_screen hdmi_info[4];
hdmi_set_info(&hdmi_info[0]);
case HDMI_720x576p_50Hz:
rc = FB_Switch_Screen(&hdmi_info[2], type);
break;
+ case HDMI_1920x1080p_50Hz:
+ rc = FB_Switch_Screen(&hdmi_info[3], type);
+ break;
default:
rc = FB_Switch_Screen(&hdmi_info[1], type);
break;