enable hdmi audio output
authorkfx <kfx@rock-chips.com>
Mon, 20 Dec 2010 12:47:31 +0000 (20:47 +0800)
committerkfx <kfx@rock-chips.com>
Mon, 20 Dec 2010 12:47:31 +0000 (20:47 +0800)
drivers/video/hdmi/chips/anx7150.c
drivers/video/hdmi/chips/anx7150.h
drivers/video/hdmi/chips/anx7150_hw.c
drivers/video/hdmi/chips/anx7150_hw.h
drivers/video/hdmi/hdmi-fb.c
drivers/video/hdmi/hdmi-sysfs.c
include/linux/hdmi.h

index 9bddc080b4dfc516c21e47cf499953989a093600..11ccb27bdc67a41a780381ae55fbd15ef5e28e06 100755 (executable)
@@ -35,10 +35,10 @@ int anx7150_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
 static int rk29_hdmi_enter(struct anx7150_dev_s *dev)\r
 {\r
        if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD) {\r
-               printk("%s, resolution = %d\n", __func__, dev->resolution_real);\r
-               if(hdmi_switch_fb(dev->resolution_real, 1) < 0)\r
+               printk("%s, resolution = %d\n", __func__, dev->resolution_set);\r
+               if(hdmi_switch_fb(dev->resolution_set, 1) < 0)\r
                        return -1;\r
-               dev->hdmi->resolution = dev->resolution_real;\r
+               dev->hdmi->resolution = dev->resolution_set;\r
                dev->rk29_output_status = RK29_OUTPUT_STATUS_HDMI;\r
        }\r
        return 0;\r
@@ -47,7 +47,7 @@ static int rk29_hdmi_exit(struct anx7150_dev_s *dev)
 {\r
        if(dev->rk29_output_status == RK29_OUTPUT_STATUS_HDMI) {\r
                printk("%s\n", __func__);\r
-               if(hdmi_switch_fb(dev->resolution_real, 0) < 0)\r
+               if(hdmi_switch_fb(dev->resolution_set, 0) < 0)\r
                        return -1;\r
                dev->rk29_output_status = RK29_OUTPUT_STATUS_LCD;\r
        }\r
index b9289337dad6b8405ca76b86e9f885018f0b355f..868eb9ae953351dfc2e64aab2552e0f2846e8f43 100755 (executable)
@@ -39,7 +39,7 @@
 #define HDMI_I2S_Fs_48000 2\r
 \r
 /* I2S default sample rate */\r
-#define HDMI_I2S_DEFAULT_Fs HDMI_I2S_Fs_48000\r
+#define HDMI_I2S_DEFAULT_Fs HDMI_I2S_Fs_44100\r
 \r
 /* ANX7150 state machine */\r
 enum{\r
index 39cd987460ecb5d1b0ea6571759f7e84d7bef3f7..61372581ebd8b85a1815fc8a2106d5552ab15ec4 100755 (executable)
@@ -38,7 +38,13 @@ struct ANX7150_video_timingtype ANX7150_video_timingtype_table =
      0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
      0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
      ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},                                                                                 //update\r
-    //576p-50hz\r
+       //1080p-60hz\r
+               {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+                0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+                0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+                0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
+                ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
+       //576p-50hz\r
     {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
      0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
      0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
@@ -62,6 +68,13 @@ struct ANX7150_video_timingtype ANX7150_video_timingtype_table =
      0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
      0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
      ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
+     \r
+       //1080p-50hz\r
+        {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
+         0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
+         0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
+         0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
+         ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
 };\r
 //#endif\r
 int anx7150_mass_read_need_delay = 0;\r
@@ -1827,7 +1840,9 @@ int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev)
         hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
         hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
         hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
-        hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
+               hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
+               hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
+               hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
         hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
         hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
         hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
@@ -1888,6 +1903,12 @@ int ANX7150_Get_Optimal_resolution(int resolution_set)
                        find_resolution = 1;\r
                }\r
                break;\r
+       case HDMI_1920x1080p_50Hz:\r
+               if(ANX7150_edid_result.supported_1080p_50Hz){\r
+                       resolution_real = HDMI_1920x1080p_50Hz;\r
+                       find_resolution = 1;\r
+               }\r
+               break;\r
        default:\r
                break;\r
        }\r
@@ -1900,6 +1921,8 @@ int ANX7150_Get_Optimal_resolution(int resolution_set)
                        resolution_real = HDMI_1280x720p_60Hz;\r
                else if(ANX7150_edid_result.supported_576p_50Hz)\r
                        resolution_real = HDMI_720x576p_50Hz;\r
+               else if(ANX7150_edid_result.supported_1080p_50Hz)\r
+                       resolution_real = HDMI_1920x1080p_50Hz;\r
                else\r
                        resolution_real = HDMI_1280x720p_50Hz;\r
        }\r
@@ -2034,6 +2057,7 @@ static int anx7150_blue_screen_format_config(struct i2c_client *client)
 static void ANX7150_Get_Video_Timing(void)\r
 {\r
     u8 i;\r
+       \r
 //#ifdef ITU656\r
     for (i = 0; i < 18; i++)\r
     {\r
@@ -2762,7 +2786,7 @@ int ANX7150_Config_Video(struct i2c_client *client)
     rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
        c |= (ANX7150_VID_CTRL_IN_EN);\r
        rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
+       msleep(200);\r
     //D("Video configure OK!\n");\r
        rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
     if (!(c & ANX7150_VID_STATUS_VID_STABLE))\r
@@ -3063,6 +3087,7 @@ u8 ANX7150_Config_Audio(struct i2c_client *client)
     {\r
         //disable super audio output\r
         hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
+               c = 0x00;\r
                rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
     }\r
 \r
@@ -3143,11 +3168,11 @@ u8 ANX7150_Config_Audio(struct i2c_client *client)
                rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
                c = 0x00;\r
                rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
-               rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-               c = (c & 0xf8) | FREQ_MCLK;\r
-               rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
        \r
         // set the relation of MCLK and Fs  xy 070117\r
+        rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
+               c = (c & 0xf8) | FREQ_MCLK;\r
+               rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
        hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
 \r
         //Enable control of ACR\r
@@ -4170,6 +4195,9 @@ void  HDMI_Set_Video_Format(u8 video_format) //CPU set the lowpower mode
                case HDMI_720x576p_50Hz:\r
                        g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
                        break;\r
+               case HDMI_1920x1080p_50Hz:\r
+                       g_video_format = ANX7150_V1920x1080p_50Hz;\r
+                       break;\r
         default:\r
             g_video_format = ANX7150_V1280x720p_50Hz;\r
             break;\r
index 0654998a78b39a4854032503a18f771810a41bfd..5c628f34b9b60389daa271ff99d749d2f192afba 100755 (executable)
@@ -56,6 +56,7 @@ struct ANX7150_video_timingtype{ //CEA-861C format
     u8 ANX7150_1280x720p_60Hz[18];//format 4\r
     u8 ANX7150_1920x1080i_60Hz[18];//format 5\r
     u8 ANX7150_720x480i_60Hz[18];//format 6 & 7\r
+    u8 ANX7150_1920x1080p_60Hz[18];\r
     //u8 ANX7150_720x240p_60Hz[18];//format 8 & 9\r
     //u8 ANX7150_2880x480i_60Hz[18];//format 10 & 11\r
     //u8 ANX7150_2880x240p_60Hz[18];//format 12 & 13\r
@@ -65,6 +66,7 @@ struct ANX7150_video_timingtype{ //CEA-861C format
     u8 ANX7150_1280x720p_50Hz[18];//format 19\r
     u8 ANX7150_1920x1080i_50Hz[18];//format 20*/\r
     u8 ANX7150_720x576i_50Hz[18];//format 21 & 22\r
+       u8 ANX7150_1920x1080p_50Hz[18];\r
     /* u8 ANX7150_720x288p_50Hz[18];//formats 23 & 24\r
     u8 ANX7150_2880x576i_50Hz[18];//formats 25 & 26\r
     u8 ANX7150_2880x288p_50Hz[18];//formats 27 & 28\r
index 2e854e12eafbeb919b29c0cb760b5352cc8337e0..b0728689e507e35850e10e372f6224f86681303a 100755 (executable)
 #define V_VD3                  576
 #define V_FP3                  5
 
+/* 1080p@50Hz Timing */
+#define OUT_CLK4               148500000
+#define H_PW4                  44
+#define H_BP4                  148
+#define H_VD4                  1920
+#define H_FP4                  528
+#define V_PW4                  5
+#define V_BP4                  35
+#define V_VD4                  1080
+#define V_FP4                  5
+
+
 extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable );
 
 static int anx7150_init(void)
@@ -61,6 +73,7 @@ static void hdmi_set_info(struct rk29fb_screen *screen)
 {
     struct rk29fb_screen *screen2 = screen + 1;
        struct rk29fb_screen *screen3 = screen + 2;
+       struct rk29fb_screen *screen4 = screen + 3;
 
     /* ****************** 720p@60Hz ******************* */
     /* screen type & face */
@@ -167,12 +180,46 @@ static void hdmi_set_info(struct rk29fb_screen *screen)
        /* Operation function*/
        screen3->init = anx7150_init;
        screen3->standby = anx7150_standby;
+       /* ****************** 1080p@50Hz ******************* */
+       /* screen type & face */
+       screen4->type = OUT_TYPE;
+       screen4->face = OUT_FACE;
+
+       /* Screen size */
+       screen4->x_res = H_VD4;
+       screen4->y_res = V_VD4;
+
+       /* Timing */
+       screen4->pixclock = OUT_CLK4;
+       screen4->left_margin = H_BP4;
+       screen4->right_margin = H_FP4;
+       screen4->hsync_len = H_PW4;
+       screen4->upper_margin = V_BP4;
+       screen4->lower_margin = V_FP4;
+       screen4->vsync_len = V_PW4;
+
+       /* Pin polarity */
+       screen4->pin_hsync = 0;
+       screen4->pin_vsync = 0;
+       screen4->pin_den = 0;
+       screen4->pin_dclk = DCLK_POL;
+
+       /* Swap rule */
+       screen4->swap_rb = SWAP_RB;
+       screen4->swap_rg = 0;
+       screen4->swap_gb = 0;
+       screen4->swap_delta = 0;
+       screen4->swap_dumy = 0;
+
+       /* Operation function*/
+       screen4->init = anx7150_init;
+       screen4->standby = anx7150_standby;
 }
 
 int hdmi_switch_fb(int resolution, int type)
 {
        int rc = 0;
-       struct rk29fb_screen hdmi_info[3];
+       struct rk29fb_screen hdmi_info[4];
 
        hdmi_set_info(&hdmi_info[0]);
 
@@ -187,6 +234,9 @@ int hdmi_switch_fb(int resolution, int type)
                case HDMI_720x576p_50Hz:
                        rc = FB_Switch_Screen(&hdmi_info[2], type);
                        break;
+               case HDMI_1920x1080p_50Hz:
+                       rc = FB_Switch_Screen(&hdmi_info[3], type);
+                       break;
                default:
                        rc = FB_Switch_Screen(&hdmi_info[1], type);
                        break;          
index 7b83c4b4ecbed9faa0dbf9c4fad94f7b6771b079..c0dc17493fe8894f517618caf90d838dd1b39071 100755 (executable)
@@ -16,6 +16,7 @@ static ssize_t hdmi_show_state_attrs(struct device *dev,
                                                "0 -- 1280x720p_50Hz\n"\r
                                                "1 -- 1280x720p_60Hz\n"\r
                                                "2 -- 720x576p_50Hz\n"\r
+                                               "3 -- 1920x1080p_50Hz\n"\r
                                                "--------------------------\n"\r
                                                "auto_switch=%d\n"\r
                                                "hdcp_on=%d\n"\r
index 648ed8d84ebb1144e3b8b3f86db19ddd4a5c7a2b..cf64568b42efacc0e94a985053dfd75720c86410 100755 (executable)
@@ -30,6 +30,8 @@ typedef int           BOOL;
 #define HDMI_1280x720p_50Hz    0\r
 #define HDMI_1280x720p_60Hz            1\r
 #define HDMI_720x576p_50Hz             2\r
+#define HDMI_1920x1080p_50Hz   3\r
+\r
 \r
 #define HDMI_MAX_ID            32\r
 \r