Put reg classes into namespaces

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22926 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC32RegisterInfo.td b/lib/Target/PowerPC/PPC32RegisterInfo.td
index c725551d7f6f0033d799647b3eb544a95128ec0b..a77590277a2503e10a2a5c05442d92db3d225a29 100644 (file)
--- a/lib/Target/PowerPC/PPC32RegisterInfo.td
+++ b/lib/Target/PowerPC/PPC32RegisterInfo.td
@@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td"
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i32, 32,
+def GPRC : RegisterClass<"PPC32", i32, 32,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@ def GPRC : RegisterClass<i32, 32,
   }];
 }
 
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
+def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;

diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.td b/lib/Target/PowerPC/PPC64RegisterInfo.td
index 974ebecb1d02c3bd55f169115e68825883ca6003..083154814a2c0217408cb4daa4bf7ae1dc298482 100644 (file)
--- a/lib/Target/PowerPC/PPC64RegisterInfo.td
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.td
@@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td"
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i64, 64,
+def GPRC : RegisterClass<"PPC64", i64, 64,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@ def GPRC : RegisterClass<i64, 64,
   }];
 }
 
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"PPC64", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
+def CRRC : RegisterClass<"PPC64", i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;