#ifndef LLVM_CODEGEN_PASSES_H
#define LLVM_CODEGEN_PASSES_H
+#include "llvm/Target/TargetMachine.h"
#include <string>
namespace llvm {
class FunctionPass;
class PassInfo;
- class TargetMachine;
class TargetLowering;
class RegisterCoalescer;
class raw_ostream;
///
FunctionPass *createLowerSubregsPass();
- /// createPostRAScheduler - under development.
- FunctionPass *createPostRAScheduler();
+ /// createPostRAScheduler - This pass performs post register allocation
+ /// scheduling.
+ FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
/// BranchFolding Pass - This pass performs machine code CFG based
/// optimizations to delete branches to branches, eliminate branches to
#ifndef LLVM_TARGET_TARGETSUBTARGET_H
#define LLVM_TARGET_TARGETSUBTARGET_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class SDep;
/// should be attempted.
virtual unsigned getSpecialAddressLatency() const { return 0; }
- // enablePostRAScheduler - Return true to enable
- // post-register-allocation scheduling.
- virtual bool enablePostRAScheduler() const { return false; }
+ // enablePostRAScheduler - If the target can benefit from post-regalloc
+ // scheduling and the specified optimization level meets the requirement
+ // return true to enable post-register-allocation scheduling.
+ virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ return false;
+ }
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None) {
- PM.add(createPostRAScheduler());
+ PM.add(createPostRAScheduler(OptLevel));
printAndVerify(PM);
}
namespace {
class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
AliasAnalysis *AA;
+ CodeGenOpt::Level OptLevel;
public:
static char ID;
- PostRAScheduler() : MachineFunctionPass(&ID) {}
+ PostRAScheduler(CodeGenOpt::Level ol) :
+ MachineFunctionPass(&ID), OptLevel(ol) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
} else {
// Check that post-RA scheduling is enabled for this target.
const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler())
+ if (!ST.enablePostRAScheduler(OptLevel))
return false;
}
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-FunctionPass *llvm::createPostRAScheduler() {
- return new PostRAScheduler();
+FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
+ return new PostRAScheduler(OptLevel);
}
const std::string & getCPUString() const { return CPUString; }
- /// enablePostRAScheduler - From TargetSubtarget, return true to
- /// enable post-RA scheduler.
- bool enablePostRAScheduler() const { return PostRAScheduler; }
+ /// enablePostRAScheduler - True at 'More' optimization except
+ /// for Thumb1.
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
+ }
/// getInstrItins - Return the instruction itineraies based on subtarget
/// selection.
/// indicating the number of scheduling cycles of backscheduling that
/// should be attempted.
unsigned getSpecialAddressLatency() const;
+
+ /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
+ /// at 'More' optimization level.
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ // FIXME: This causes llvm to miscompile itself on i386. :-(
+ return false/*OptLevel >= CodeGenOpt::Default*/;
+ }
};
} // End llvm namespace