//
// Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
//
-def CortexA8Itineraries : ProcessorItineraries<
+def CortexA8Itineraries : MultiIssueItineraries<
+ 2, // IssueWidth
+ -1, // MinLatency - OperandCycles are interpreted as MinLatency.
+ 2, // LoadLatency - overriden by OperandCycles.
+ 10, // HighLatency - currently unused.
[A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
[], [
// Two fully-pipelined integer ALU pipelines
// Bypasses
def A9_LdBypass : Bypass;
-def CortexA9Itineraries : ProcessorItineraries<
+def CortexA9Itineraries : MultiIssueItineraries<
+ 2, // IssueWidth - FIXME: A9_Issue0, A9_Issue1 are now redundant.
+ 0, // MinLatency - FIXME: for misched, remove InstrStage for OOO operations.
+ 2, // LoadLatency - optimistic, assumes bypass, overriden by OperandCycles.
+ 10, // HighLatency - currently unused.
[A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
[A9_LdBypass], [
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString);
- // After parsing Itineraries, set ItinData.IssueWidth.
- computeIssueWidth();
-
if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
// FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
// Darwin-EABI conforms to AACPS but not the rest of EABI.
return 10;
}
-void ARMSubtarget::computeIssueWidth() {
- unsigned allStage1Units = 0;
- for (const InstrItinerary *itin = InstrItins.Itineraries;
- itin->FirstStage != ~0U; ++itin) {
- const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
- allStage1Units |= IS->getUnits();
- }
- InstrItins.Props.IssueWidth = 0;
- while (allStage1Units) {
- ++InstrItins.Props.IssueWidth;
- // clear the lowest bit
- allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
- }
- assert(InstrItins.Props.IssueWidth <= 2 &&
- "itinerary bug, too many stage 1 units");
-}
-
bool ARMSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,