#include "llvm/Instructions.h"
#include "llvm/Support/LeakDetector.h"
#include "llvm/Support/GraphWriter.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/Config/config.h"
#include <fstream>
#include <iostream>
namespace {
- struct Printer : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN Printer : public MachineFunctionPass {
std::ostream *OS;
const std::string Banner;
}
namespace {
- struct Deleter : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN Deleter : public MachineFunctionPass {
const char *getPassName() const { return "Machine Code Deleter"; }
bool runOnMachineFunction(MachineFunction &MF) {
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/Visibility.h"
using namespace llvm;
namespace {
- struct PEI : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN PEI : public MachineFunctionPass {
const char *getPassName() const {
return "Prolog/Epilog Insertion & Frame Finalization";
}
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include <algorithm>
#include <cmath>
#include <iostream>
static unsigned numIterations = 0;
static unsigned numIntervals = 0;
- struct RA : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN RA : public MachineFunctionPass {
typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
typedef std::vector<IntervalPtr> IntervalPtrs;
private:
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
Statistic<> NumStores("ra-simple", "Number of stores added");
Statistic<> NumLoads ("ra-simple", "Number of loads added");
- class RegAllocSimple : public MachineFunctionPass {
+ class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/ADT/Statistic.h"
#include <climits>
#include <iostream>
/// ScheduleDAGList - The actual list scheduler implementation. This supports
/// top-down scheduling.
///
-class ScheduleDAGList : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGList : public ScheduleDAG {
private:
/// AvailableQueue - The priority queue to use for the available SUnits.
///
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/ADT/Statistic.h"
#include <climits>
#include <iostream>
/// implementation. This supports both top-down and bottom-up scheduling.
///
-class ScheduleDAGRRList : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
private:
/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
/// it is top-down.
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include <algorithm>
#include <iostream>
using namespace llvm;
///
/// ScheduleDAGSimple - Simple two pass scheduler.
///
-class ScheduleDAGSimple : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGSimple : public ScheduleDAG {
private:
bool NoSched; // Just do a BFS schedule, nothing fancy
bool NoItins; // Don't use itineraries?
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
"Number of instructions promoted to 3-address");
- struct TwoAddressInstructionPass : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN TwoAddressInstructionPass
+ : public MachineFunctionPass {
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
/// runOnMachineFunction - pass entry point
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
Spiller::~Spiller() {}
namespace {
- struct SimpleSpiller : public Spiller {
+ struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
};
}
/// block to attempt to keep spills in registers as much as possible for
/// blocks that have low register pressure (the vreg may be spilled due to
/// register pressure in other blocks).
- class LocalSpiller : public Spiller {
+ class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
const MRegisterInfo *MRI;
const TargetInstrInfo *TII;
public:
/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
/// entries. The predicate 'canClobberPhysReg()' checks this bit and
/// addAvailable sets it if.
-class AvailableSpills {
+namespace {
+class VISIBILITY_HIDDEN AvailableSpills {
const MRegisterInfo *MRI;
const TargetInstrInfo *TII;
/// for this slot lives in (as the previous value is dead now).
void ModifyStackSlot(int Slot);
};
+}
/// ClobberPhysRegOnly - This is called when the specified physreg changes
/// value. We use this to invalidate any info about stuff we thing lives in it.
/// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
/// is reused instead of reloaded.
- class ReuseInfo {
+ class VISIBILITY_HIDDEN ReuseInfo {
MachineInstr &MI;
std::vector<ReusedOp> Reuses;
public:
projects / oota-llvm.git / commitdiff