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Expand unaligned i16 loads/stores for the Mips backend.
author
Akira Hatanaka
<ahatanaka@mips.com>
Sat, 2 Jun 2012 00:02:45 +0000
(
00:02
+0000)
committer
Akira Hatanaka
<ahatanaka@mips.com>
Sat, 2 Jun 2012 00:02:45 +0000
(
00:02
+0000)
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/Mips/MipsISelLowering.cpp
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diff --git
a/lib/Target/Mips/MipsISelLowering.cpp
b/lib/Target/Mips/MipsISelLowering.cpp
index 6ea2692d6f80eb3500416b852dada95774c07f3d..d0ea2185e0c8a02faa1f61041c1b42458294482f 100644
(file)
--- a/
lib/Target/Mips/MipsISelLowering.cpp
+++ b/
lib/Target/Mips/MipsISelLowering.cpp
@@
-292,7
+292,6
@@
bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
switch (SVT) {
case MVT::i64:
case MVT::i32:
- case MVT::i16:
return true;
case MVT::f32:
return Subtarget->hasMips32r2Or64();