(shl GPR:$Rm, (i32 8))), i16),
(REVSH GPR:$Rm)>;
+def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
+ (and (srl GPR:$Rm, (i32 8)), 0xFF)),
+ (REVSH GPR:$Rm)>;
+
// Need the AddedComplexity or else MOVs + REV would be chosen.
let AddedComplexity = 5 in
def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
(shl rGPR:$Rm, (i32 8))), i16),
(t2REVSH rGPR:$Rm)>;
+def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
+ (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
+ (t2REVSH rGPR:$Rm)>;
+
def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
def t2PKHBT : T2ThreeReg<
%conv8 = ashr exact i32 %sext, 16
ret i32 %conv8
}
+
+; rdar://9609059
+define i32 @test5(i32 %i) nounwind readnone {
+entry:
+; CHECK: test5
+; CHECK: revsh r0, r0
+ %shl = shl i32 %i, 24
+ %shr = ashr exact i32 %shl, 16
+ %shr23 = lshr i32 %i, 8
+ %and = and i32 %shr23, 255
+ %or = or i32 %shr, %and
+ ret i32 %or
+}