Merge remote-tracking branches 'spi/topic/mxs', 'spi/topic/pxa', 'spi/topic/rockchip...

diff --combined drivers/spi/Kconfig
index 400c34468cad29d582bcaa08466b3299d2ba22e9,84e7c9e6ccef0562c3133c47e171f23ee9af4a17,84e7c9e6ccef0562c3133c47e171f23ee9af4a17,84e7c9e6ccef0562c3133c47e171f23ee9af4a17,de2d33dea8b85c2218a0f693e1add66cf43f1d6a,84e7c9e6ccef0562c3133c47e171f23ee9af4a17..99829985c1a194ebe6edc0e73912077bade693d3
--- 1/drivers/spi/Kconfig
--- 2/drivers/spi/Kconfig
--- 3/drivers/spi/Kconfig
--- 4/drivers/spi/Kconfig
--- 5/drivers/spi/Kconfig
--- 6/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@@@@@@ -225,13 -225,6 -225,6 -225,6 -225,6 -225,6 +225,13 @@@@@@@ config SPI_GPI
          GPIO operations, you should be able to leverage that for better
          speed with a custom version of this driver; see the source code.
      
 +++++config SPI_IMG_SPFI
 +++++  tristate "IMG SPFI controller"
 +++++  depends on MIPS || COMPILE_TEST
 +++++  help
 +++++    This enables support for the SPFI master controller found on
 +++++    IMG SoCs.
 +++++
      config SPI_IMX
        tristate "Freescale i.MX SPI controllers"
        depends on ARCH_MXC || COMPILE_TEST
@@@@@@@ -308,14 -301,6 -301,6 -301,6 -301,6 -301,6 +308,14 @@@@@@@ config SPI_FSL_ESP
          From MPC8536, 85xx platform uses the controller, and all P10xx,
          P20xx, P30xx,P40xx, P50xx uses this controller.
      
 +++++config SPI_MESON_SPIFC
 +++++  tristate "Amlogic Meson SPIFC controller"
 +++++  depends on ARCH_MESON || COMPILE_TEST
 +++++  select REGMAP_MMIO
 +++++  help
 +++++    This enables master mode support for the SPIFC (SPI flash
 +++++    controller) available in Amlogic Meson SoCs.
 +++++
      config SPI_OC_TINY
        tristate "OpenCores tiny SPI"
        depends on GPIOLIB
@@@@@@@ -459,7 -444,7 -444,7 -444,7 -444,7 -444,7 +459,7 @@@@@@@ config SPI_S3C24XX_FI
      
      config SPI_S3C64XX
        tristate "Samsung S3C64XX series type SPI"
---- -  depends on PLAT_SAMSUNG
++++ +  depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
        select S3C64XX_PL080 if ARCH_S3C64XX
        help
          SPI driver for Samsung S3C64XX and newer SoCs.

diff --combined drivers/spi/spi-rockchip.c
index 87bc16f491f0ce8e3d78733d434a67189632e756,f96ea8a38d640f988a797ecd448b2c9c64e9a8ed,87bc16f491f0ce8e3d78733d434a67189632e756,08897d34ce33cf05eab685fda0263b2fc28eae3f,f96ea8a38d640f988a797ecd448b2c9c64e9a8ed,f96ea8a38d640f988a797ecd448b2c9c64e9a8ed..80637e9406e2c56cd83f855628e211837b77a28b
--- 1/drivers/spi/spi-rockchip.c
--- 2/drivers/spi/spi-rockchip.c
--- 3/drivers/spi/spi-rockchip.c
--- 4/drivers/spi/spi-rockchip.c
--- 5/drivers/spi/spi-rockchip.c
--- 6/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@@@@@@ -145,9 -145,6 -145,9 -145,6 -145,6 -145,6 +145,9 @@@@@@@
      #define RXBUSY                                            (1 << 0)
      #define TXBUSY                                            (1 << 1)
      
 + +++/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 + +++#define MAX_SCLK_OUT              50000000
 + +++
      enum rockchip_ssi_type {
        SSI_MOTO_SPI = 0,
        SSI_TI_SSP,
@@@@@@@ -328,8 -325,6 -328,8 -325,6 -325,6 -325,6 +328,8 @@@@@@@ static int rockchip_spi_unprepare_messa
      
        spin_unlock_irqrestore(&rs->lock, flags);
      
 + +++  spi_enable_chip(rs, 0);
 + +++
        return 0;
      }
      
@@@@@@@ -386,8 -381,6 -386,8 -381,6 -381,6 -381,6 +386,8 @@@@@@@ static int rockchip_spi_pio_transfer(st
        if (rs->tx)
                wait_for_idle(rs);
      
 + +++  spi_enable_chip(rs, 0);
 + +++
        return 0;
      }
      
@@@@@@@ -399,10 -392,8 -399,10 -392,8 -392,8 -392,8 +399,10 @@@@@@@ static void rockchip_spi_dma_rxcb(void 
        spin_lock_irqsave(&rs->lock, flags);
      
        rs->state &= ~RXBUSY;
 - ---  if (!(rs->state & TXBUSY))
 + +++  if (!(rs->state & TXBUSY)) {
 + +++          spi_enable_chip(rs, 0);
                spi_finalize_current_transfer(rs->master);
 + +++  }
      
        spin_unlock_irqrestore(&rs->lock, flags);
      }
@@@@@@@ -418,10 -409,8 -418,10 -409,8 -409,8 -409,8 +418,10 @@@@@@@ static void rockchip_spi_dma_txcb(void 
        spin_lock_irqsave(&rs->lock, flags);
      
        rs->state &= ~TXBUSY;
 - ---  if (!(rs->state & RXBUSY))
 + +++  if (!(rs->state & RXBUSY)) {
 + +++          spi_enable_chip(rs, 0);
                spi_finalize_current_transfer(rs->master);
 + +++  }
      
        spin_unlock_irqrestore(&rs->lock, flags);
      }
@@@@@@@ -507,19 -496,12 -507,19 -496,12 -496,12 -496,12 +507,19 @@@@@@@ static void rockchip_spi_config(struct 
                        dmacr |= RF_DMA_EN;
        }
      
 + +++  if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 + +++          rs->speed = MAX_SCLK_OUT;
 + +++
 + +++  /* the minimum divsor is 2 */
 + +++  if (rs->max_freq < 2 * rs->speed) {
 + +++          clk_set_rate(rs->spiclk, 2 * rs->speed);
 + +++          rs->max_freq = clk_get_rate(rs->spiclk);
 + +++  }
 + +++
        /* div doesn't support odd number */
        div = max_t(u32, rs->max_freq / rs->speed, 1);
        div = (div + 1) & 0xfffe;
      
 - ---  spi_enable_chip(rs, 0);
 - ---
        writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
      
        writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
@@@@@@@ -533,6 -515,8 -533,6 -515,8 -515,8 -515,8 +533,6 @@@@@@@
        spi_set_clk(rs, div);
      
        dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 - ---
 - ---  spi_enable_chip(rs, 1);
      }
      
      static int rockchip_spi_transfer_one(
@@@@@@@ -540,7 -524,7 -540,7 -524,7 -524,7 -524,7 +540,7 @@@@@@@
                struct spi_device *spi,
                struct spi_transfer *xfer)
      {
 - ---  int ret = 0;
 + +++  int ret = 1;
        struct rockchip_spi *rs = spi_master_get_devdata(master);
      
        WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
@@@@@@@ -572,27 -556,17 -572,27 -556,17 -556,17 -556,17 +572,27 @@@@@@@
                rs->tmode = CR0_XFM_RO;
      
        /* we need prepare dma before spi was enabled */
 - ---  if (master->can_dma && master->can_dma(master, spi, xfer)) {
 + +++  if (master->can_dma && master->can_dma(master, spi, xfer))
                rs->use_dma = 1;
 - ---          rockchip_spi_prepare_dma(rs);
 - ---  } else {
 + +++  else
                rs->use_dma = 0;
 - ---  }
      
        rockchip_spi_config(rs);
      
 - ---  if (!rs->use_dma)
 + +++  if (rs->use_dma) {
 + +++          if (rs->tmode == CR0_XFM_RO) {
 + +++                  /* rx: dma must be prepared first */
 + +++                  rockchip_spi_prepare_dma(rs);
 + +++                  spi_enable_chip(rs, 1);
 + +++          } else {
 + +++                  /* tx or tr: spi must be enabled first */
 + +++                  spi_enable_chip(rs, 1);
 + +++                  rockchip_spi_prepare_dma(rs);
 + +++          }
 + +++  } else {
 + +++          spi_enable_chip(rs, 1);
                ret = rockchip_spi_pio_transfer(rs);
 + +++  }
      
        return ret;
      }
@@@@@@@ -749,8 -723,8 -749,8 -723,6 -723,8 -723,8 +749,6 @@@@@@@ static int rockchip_spi_remove(struct p
        if (rs->dma_rx.ch)
                dma_release_channel(rs->dma_rx.ch);
      
--- --  spi_master_put(master);
--- --
        return 0;
      }
      

diff --combined drivers/spi/spi-sirf.c
index f63de781c72959c7c29b8fb2bb215f4e33b28f87,39e2c0a55a2865acc6c50354cf90fa27263bc922,39e2c0a55a2865acc6c50354cf90fa27263bc922,39e2c0a55a2865acc6c50354cf90fa27263bc922,39e2c0a55a2865acc6c50354cf90fa27263bc922,0a96a65f580fbe82ccf1f8b3bd99924de425230e..73a88b33f810d61ea30d68aedddfcb303c7f7345
--- 1/drivers/spi/spi-sirf.c
--- 2/drivers/spi/spi-sirf.c
--- 3/drivers/spi/spi-sirf.c
--- 4/drivers/spi/spi-sirf.c
--- 5/drivers/spi/spi-sirf.c
--- 6/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@@@@@@ -23,6 -23,6 -23,6 -23,6 -23,6 -23,7 +23,7 @@@@@@@
      #include <linux/dmaengine.h>
      #include <linux/dma-direction.h>
      #include <linux/dma-mapping.h>
+++++ #include <linux/reset.h>
      
      #define DRIVER_NAME "sirfsoc_spi"
      
@@@@@@@ -134,6 -134,6 -134,6 -134,6 -134,6 -135,7 +135,7 @@@@@@@
        ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
      
      #define SIRFSOC_MAX_CMD_BYTES     4
+++++ #define SIRFSOC_SPI_DEFAULT_FRQ 1000000
      
      struct sirfsoc_spi {
        struct spi_bitbang bitbang;
@@@@@@@ -562,9 -562,9 -562,9 -562,9 -562,9 -564,9 +564,9 @@@@@@@ spi_sirfsoc_setup_transfer(struct spi_d
      
        sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
        txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 -----                                     sspi->word_width;
 +++++                                     (sspi->word_width >> 1);
        rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 -----                                     sspi->word_width;
 +++++                                     (sspi->word_width >> 1);
      
        if (!(spi->mode & SPI_CS_HIGH))
                regval |= SIRFSOC_SPI_CS_IDLE_STAT;
@@@@@@@ -629,9 -629,9 -629,9 -629,9 -629,9 -631,6 +631,6 @@@@@@@ static int spi_sirfsoc_setup(struct spi
      {
        struct sirfsoc_spi *sspi;
      
-----   if (!spi->max_speed_hz)
-----           return -EINVAL;
----- 
        sspi = spi_master_get_devdata(spi->master);
      
        if (spi->cs_gpio == -ENOENT)
@@@@@@@ -649,6 -649,6 -649,6 -649,6 -649,6 -648,12 +648,12 @@@@@@@ static int spi_sirfsoc_probe(struct pla
        int irq;
        int i, ret;
      
+++++   ret = device_reset(&pdev->dev);
+++++   if (ret) {
+++++           dev_err(&pdev->dev, "SPI reset failed!\n");
+++++           return ret;
+++++   }
+++++ 
        master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
        if (!master) {
                dev_err(&pdev->dev, "Unable to allocate SPI master\n");
@@@@@@@ -683,6 -683,6 -683,6 -683,6 -683,6 -688,7 +688,7 @@@@@@@
        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
        master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
                                        SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
+++++   master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
        sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
      
        /* request DMA channels */