Apply this patch:

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37240 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 818fcd5f59ad21467f3b3e27266654e87e4f433e..9723c7c8c2aff09ccbeb74a0aaacddedc0957e0c 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -222,7 +222,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
     // First set operation action for all vector types to expand. Then we
     // will selectively turn on ones that can be effectively codegen'd.
     for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
-         VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+         VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
       // add/sub are legal for all supported vector VT's.
       setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
       setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);