// IT block condition mask
def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask";
+ let DecoderMethod = "DecodeITMask";
}
// Shifted operands. No register controlled shifts for Thumb2.
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
return S;
}
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+ if (Mask == 0) {
+ Mask = 0x8;
+ CHECK(S, Unpredictable);
+ }
+ Inst.addOperand(MCOperand::CreateImm(Mask));
+ return S;
+}
+