--- /dev/null
+//===- PPC32.td - Describe the PowerPC Target Machine ------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+// Get the target-independent interfaces which we are implementing...
+//
+include "../Target.td"
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "PPC32RegisterInfo.td"
+include "PowerPCInstrInfo.td"
+
+def PowerPCInstrInfo : InstrInfo {
+ let PHIInst = PHI;
+
+ let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type",
+ "Arg3Type", "Arg4Type", "VMX", "PPC64"];
+ let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+}
+
+def PPC32 : Target {
+ // Pointers on PPC32 are 32-bits in size.
+ let PointerType = i32;
+
+ // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+ // calls
+ let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+ R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+ F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+ F30, F31, CR2, CR3, CR4, LR];
+
+ // Pull in Instruction Info:
+ let InstructionSet = PowerPCInstrInfo;
+}
#define DEBUG_TYPE "asmprinter"
#include "PowerPC.h"
-#include "PowerPCInstrInfo.h"
-#include "PowerPCTargetMachine.h"
+#include "PPC32TargetMachine.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "Support/CommandLine.h"
#include "Support/Debug.h"
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
- struct PowerPCAsmPrinter : public AsmPrinter {
+ struct PPC32AsmPrinter : public AsmPrinter {
std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
std::set<std::string> Strings;
- PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
+ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM)
: AsmPrinter(O, TM), LabelNumber(0) {
UsesUnderscorePrefix = 1;
}
unsigned LabelNumber;
virtual const char *getPassName() const {
- return "PowerPC Assembly Printer";
+ return "PPC32 Assembly Printer";
}
- PowerPCTargetMachine &getTM() {
- return static_cast<PowerPCTargetMachine&>(TM);
+ PPC32TargetMachine &getTM() {
+ return static_cast<PPC32TargetMachine&>(TM);
}
/// printInstruction - This method is automatically generated by tablegen
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form or not.
///
-FunctionPass *llvm::createPPCAsmPrinter(std::ostream &o,TargetMachine &tm) {
- return new PowerPCAsmPrinter(o, tm);
+FunctionPass *llvm::createPPC32AsmPrinter(std::ostream &o, TargetMachine &tm) {
+ return new PPC32AsmPrinter(o, tm);
}
// Include the auto-generated portion of the assembly writer
// Print a constant value or values, with the appropriate storage class as a
// prefix.
-void PowerPCAsmPrinter::emitGlobalConstant(const Constant *CV) {
+void PPC32AsmPrinter::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (CV->isNullValue()) {
/// used to print out constants which have been "spilled to memory" by
/// the code generator.
///
-void PowerPCAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
+void PPC32AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
-bool PowerPCAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+bool PPC32AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
setupMachineFunction(MF);
O << "\n\n";
return false;
}
-void PowerPCAsmPrinter::printOp(const MachineOperand &MO,
- bool LoadAddrOp /* = false */) {
+void PPC32AsmPrinter::printOp(const MachineOperand &MO,
+ bool LoadAddrOp /* = false */) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
int new_symbol;
}
}
-void PowerPCAsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) {
+void PPC32AsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///
-void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
if (printInstruction(MI))
return; // Printer was automatically generated
}
}
-bool PowerPCAsmPrinter::doFinalization(Module &M) {
+bool PPC32AsmPrinter::doFinalization(Module &M) {
const TargetData &TD = TM.getTargetData();
std::string CurSection;
-//===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===//
+//===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
//
// The LLVM Compiler Infrastructure
//
unsigned GlobalBaseReg;
bool GlobalBaseInitialized;
- ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
+ ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
F(0), BB(0) {}
bool doInitialization(Module &M) {
/// high 32 bits of the long value, and the regNum+1 is the low 32 bits.
///
unsigned makeAnotherReg(const Type *Ty) {
- assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
+ assert(dynamic_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have PPC reg info??");
- const PowerPCRegisterInfo *PPCRI =
- static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
+ const PPC32RegisterInfo *PPCRI =
+ static_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) {
const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
// Create the upper part
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
- Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
+ Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
--- /dev/null
+//===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+include "PowerPCRegisterInfo.td"
+
+/// Register classes
+// Allocate volatiles first
+// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
+def GPRC : RegisterClass<i32, 8,
+ [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+ R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+ R16, R15, R14, R13, R0, R1, LR]>
+{
+ let Methods = [{
+ iterator allocation_order_begin(MachineFunction &MF) const {
+ return begin() + (AIX ? 1 : 0);
+ }
+ iterator allocation_order_end(MachineFunction &MF) const {
+ if (hasFP(MF))
+ return end()-4;
+ else
+ return end()-3;
+ }
+ }];
+}
+
+def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+ F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+ F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
+def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
#define DEBUG_TYPE "asmprinter"
#include "PowerPC.h"
-#include "PowerPCInstrInfo.h"
-#include "PowerPCTargetMachine.h"
+#include "PPC32TargetMachine.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "Support/CommandLine.h"
#include "Support/Debug.h"
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
- struct PowerPCAsmPrinter : public AsmPrinter {
+ struct PPC32AsmPrinter : public AsmPrinter {
std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
std::set<std::string> Strings;
- PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
+ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM)
: AsmPrinter(O, TM), LabelNumber(0) {
UsesUnderscorePrefix = 1;
}
unsigned LabelNumber;
virtual const char *getPassName() const {
- return "PowerPC Assembly Printer";
+ return "PPC32 Assembly Printer";
}
- PowerPCTargetMachine &getTM() {
- return static_cast<PowerPCTargetMachine&>(TM);
+ PPC32TargetMachine &getTM() {
+ return static_cast<PPC32TargetMachine&>(TM);
}
/// printInstruction - This method is automatically generated by tablegen
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form or not.
///
-FunctionPass *llvm::createPPCAsmPrinter(std::ostream &o,TargetMachine &tm) {
- return new PowerPCAsmPrinter(o, tm);
+FunctionPass *llvm::createPPC32AsmPrinter(std::ostream &o, TargetMachine &tm) {
+ return new PPC32AsmPrinter(o, tm);
}
// Include the auto-generated portion of the assembly writer
// Print a constant value or values, with the appropriate storage class as a
// prefix.
-void PowerPCAsmPrinter::emitGlobalConstant(const Constant *CV) {
+void PPC32AsmPrinter::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (CV->isNullValue()) {
/// used to print out constants which have been "spilled to memory" by
/// the code generator.
///
-void PowerPCAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
+void PPC32AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
-bool PowerPCAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+bool PPC32AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
setupMachineFunction(MF);
O << "\n\n";
return false;
}
-void PowerPCAsmPrinter::printOp(const MachineOperand &MO,
- bool LoadAddrOp /* = false */) {
+void PPC32AsmPrinter::printOp(const MachineOperand &MO,
+ bool LoadAddrOp /* = false */) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
int new_symbol;
}
}
-void PowerPCAsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) {
+void PPC32AsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///
-void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
if (printInstruction(MI))
return; // Printer was automatically generated
}
}
-bool PowerPCAsmPrinter::doFinalization(Module &M) {
+bool PPC32AsmPrinter::doFinalization(Module &M) {
const TargetData &TD = TM.getTargetData();
std::string CurSection;
--- /dev/null
+//===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the PowerPC implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPC32InstrInfo.h"
+#include "PPC32GenInstrInfo.inc"
+#include "PowerPC.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include <iostream>
+using namespace llvm;
+
+PPC32InstrInfo::PPC32InstrInfo()
+ : TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {}
+
+bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ MachineOpCode oc = MI.getOpcode();
+ if (oc == PPC::OR) { // or r1, r2, r2
+ assert(MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ MI.getOperand(2).isRegister() &&
+ "invalid PPC OR instruction!");
+ if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ } else if (oc == PPC::ADDI) { // addi r1, r2, 0
+ assert(MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(2).isImmediate() &&
+ "invalid PPC ADDI instruction!");
+ if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ } else if (oc == PPC::FMR) { // fmr r1, r2
+ assert(MI.getNumOperands() == 2 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ "invalid PPC FMR instruction");
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ return false;
+}
--- /dev/null
+//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the PowerPC implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef POWERPC32_INSTRUCTIONINFO_H
+#define POWERPC32_INSTRUCTIONINFO_H
+
+#include "PowerPCInstrInfo.h"
+#include "PPC32RegisterInfo.h"
+
+namespace llvm {
+
+class PPC32InstrInfo : public TargetInstrInfo {
+ const PPC32RegisterInfo RI;
+public:
+ PPC32InstrInfo();
+
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
+ /// such, whenever a client has an instance of instruction info, it should
+ /// always be able to get register info as well (through this method).
+ ///
+ virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+
+ //
+ // Return true if the instruction is a register to register move and
+ // leave the source and dest operands in the passed parameters.
+ //
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const;
+
+ static unsigned invertPPCBranchOpcode(unsigned Opcode) {
+ switch (Opcode) {
+ default: assert(0 && "Unknown PPC branch opcode!");
+ case PPC::BEQ: return PPC::BNE;
+ case PPC::BNE: return PPC::BEQ;
+ case PPC::BLT: return PPC::BGE;
+ case PPC::BGE: return PPC::BLT;
+ case PPC::BGT: return PPC::BLE;
+ case PPC::BLE: return PPC::BGT;
+ }
+ }
+};
+
+}
+
+#endif
--- /dev/null
+//===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the PowerPC32 implementation of the MRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "reginfo"
+#include "PowerPC.h"
+#include "PowerPCInstrBuilder.h"
+#include "PPC32RegisterInfo.h"
+#include "llvm/Constants.h"
+#include "llvm/Type.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/Target/TargetFrameInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "Support/CommandLine.h"
+#include "Support/Debug.h"
+#include "Support/STLExtras.h"
+#include <cstdlib>
+#include <iostream>
+using namespace llvm;
+
+namespace llvm {
+ // Switch toggling compilation for AIX
+ extern cl::opt<bool> AIX;
+}
+
+PPC32RegisterInfo::PPC32RegisterInfo()
+ : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
+ ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
+ ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
+ ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
+ ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
+ ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
+ ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
+ ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
+ ImmToIdxMap[PPC::ADDI] = PPC::ADD;
+}
+
+static unsigned getIdx(const TargetRegisterClass *RC) {
+ if (RC == PPC32::GPRCRegisterClass) {
+ switch (RC->getSize()) {
+ default: assert(0 && "Invalid data size!");
+ case 1: return 0;
+ case 2: return 1;
+ case 4: return 2;
+ }
+ } else if (RC == PPC32::FPRCRegisterClass) {
+ switch (RC->getSize()) {
+ default: assert(0 && "Invalid data size!");
+ case 4: return 3;
+ case 8: return 4;
+ }
+ }
+ std::cerr << "Invalid register class to getIdx()!\n";
+ abort();
+}
+
+void
+PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, int FrameIdx) const {
+ const TargetRegisterClass *RC = getRegClass(SrcReg);
+ static const unsigned Opcode[] = {
+ PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
+ };
+
+ unsigned OC = Opcode[getIdx(RC)];
+ if (SrcReg == PPC::LR) {
+ BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
+ } else {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
+ }
+}
+
+void
+PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx) const{
+ static const unsigned Opcode[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
+ };
+ const TargetRegisterClass *RC = getRegClass(DestReg);
+ unsigned OC = Opcode[getIdx(RC)];
+ if (DestReg == PPC::LR) {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
+ BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
+ } else {
+ BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
+ addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
+ }
+}
+
+void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const {
+ MachineInstr *I;
+
+ if (RC == PPC32::GPRCRegisterClass) {
+ BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (RC == PPC32::FPRCRegisterClass) {
+ BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
+ } else {
+ std::cerr << "Attempt to copy register that is not GPR or FPR";
+ abort();
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// Stack Frame Processing methods
+//===----------------------------------------------------------------------===//
+
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register. This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+//
+static bool hasFP(MachineFunction &MF) {
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ return MFI->hasVarSizedObjects();
+}
+
+void PPC32RegisterInfo::
+eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
+ if (hasFP(MF)) {
+ // If we have a frame pointer, convert as follows:
+ // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
+ // ADJCALLSTACKUP -> addi, r1, r1, amount
+ MachineInstr *Old = I;
+ unsigned Amount = Old->getOperand(0).getImmedValue();
+ if (Amount != 0) {
+ // We need to keep the stack aligned properly. To do this, we round the
+ // amount of space needed for the outgoing arguments up to the next
+ // alignment boundary.
+ unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+ Amount = (Amount+Align-1)/Align*Align;
+
+ // Replace the pseudo instruction with a new instruction...
+ if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
+ MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
+ .addSImm(-Amount));
+ } else {
+ assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
+ MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
+ .addSImm(Amount));
+ }
+ }
+ }
+ MBB.erase(I);
+}
+
+void
+PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+ unsigned i = 0;
+ MachineInstr &MI = *II;
+ MachineBasicBlock &MBB = *MI.getParent();
+ MachineFunction &MF = *MBB.getParent();
+
+ while (!MI.getOperand(i).isFrameIndex()) {
+ ++i;
+ assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
+ }
+
+ int FrameIndex = MI.getOperand(i).getFrameIndex();
+
+ // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
+ MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
+
+ // Take into account whether it's an add or mem instruction
+ unsigned OffIdx = (i == 2) ? 1 : 2;
+
+ // Now add the frame object offset to the offset from r1.
+ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
+ MI.getOperand(OffIdx).getImmedValue();
+
+ // If we're not using a Frame Pointer that has been set to the value of the
+ // SP before having the stack size subtracted from it, then add the stack size
+ // to Offset to get the correct offset.
+ Offset += MF.getFrameInfo()->getStackSize();
+
+ if (Offset > 32767 || Offset < -32768) {
+ // Insert a set of r0 with the full offset value before the ld, st, or add
+ MachineBasicBlock *MBB = MI.getParent();
+ MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
+ MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(Offset));
+ // convert into indexed form of the instruction
+ // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
+ // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
+ unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
+ assert(NewOpcode && "No indexed form of load or store available!");
+ MI.setOpcode(NewOpcode);
+ MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
+ MI.SetMachineOperandReg(2, PPC::R0);
+ } else {
+ MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
+ }
+}
+
+
+void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
+ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
+ MachineBasicBlock::iterator MBBI = MBB.begin();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineInstr *MI;
+
+ // Get the number of bytes to allocate from the FrameInfo
+ unsigned NumBytes = MFI->getStackSize();
+
+ // If we have calls, we cannot use the red zone to store callee save registers
+ // and we must set up a stack frame, so calculate the necessary size here.
+ if (MFI->hasCalls()) {
+ // We reserve argument space for call sites in the function immediately on
+ // entry to the current function. This eliminates the need for add/sub
+ // brackets around call sites.
+ NumBytes += MFI->getMaxCallFrameSize();
+ }
+
+ // Do we need to allocate space on the stack?
+ if (NumBytes == 0) return;
+
+ // Add the size of R1 to NumBytes size for the store of R1 to the bottom
+ // of the stack and round the size to a multiple of the alignment.
+ unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+ unsigned R1Size = getRegClass(PPC::R1)->getSize();
+ unsigned R31Size = getRegClass(PPC::R31)->getSize();
+ unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size;
+ NumBytes = (NumBytes+Size+Align-1)/Align*Align;
+
+ // Update frame info to pretend that this is part of the stack...
+ MFI->setStackSize(NumBytes);
+
+ // adjust stack pointer: r1 -= numbytes
+ if (NumBytes <= 32768) {
+ MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ } else {
+ int NegNumbytes = -NumBytes;
+ MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes & 0xFFFF);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ MBB.insert(MBBI, MI);
+ }
+
+ if (hasFP(MF)) {
+ MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ }
+}
+
+void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ MachineInstr *MI;
+ assert(MBBI->getOpcode() == PPC::BLR &&
+ "Can only insert epilog into returning blocks");
+
+ // Get the number of bytes allocated from the FrameInfo...
+ unsigned NumBytes = MFI->getStackSize();
+
+ if (NumBytes != 0) {
+ if (hasFP(MF)) {
+ MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
+ MBB.insert(MBBI, MI);
+ MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(4).addReg(PPC::R31);
+ MBB.insert(MBBI, MI);
+ }
+ MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
+ MBB.insert(MBBI, MI);
+ }
+}
+
+#include "PPC32GenRegisterInfo.inc"
+
+const TargetRegisterClass*
+PPC32RegisterInfo::getRegClassForType(const Type* Ty) const {
+ switch (Ty->getTypeID()) {
+ default: assert(0 && "Invalid type to getClass!");
+ case Type::LongTyID:
+ case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
+ case Type::BoolTyID:
+ case Type::SByteTyID:
+ case Type::UByteTyID:
+ case Type::ShortTyID:
+ case Type::UShortTyID:
+ case Type::IntTyID:
+ case Type::UIntTyID:
+ case Type::PointerTyID: return &GPRCInstance;
+
+ case Type::FloatTyID:
+ case Type::DoubleTyID: return &FPRCInstance;
+ }
+}
+
--- /dev/null
+//===- PPC32RegisterInfo.h - PowerPC32 Register Information Impl -*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the PowerPC implementation of the MRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef POWERPC32_REGISTERINFO_H
+#define POWERPC32_REGISTERINFO_H
+
+#include "PowerPC.h"
+#include "PPC32GenRegisterInfo.h.inc"
+#include <map>
+
+namespace llvm {
+
+class Type;
+
+class PPC32RegisterInfo : public PPC32GenRegisterInfo {
+ std::map<unsigned, unsigned> ImmToIdxMap;
+public:
+ PPC32RegisterInfo();
+ const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+
+ /// Code Generation virtual methods...
+ void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIndex) const;
+
+ void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex) const;
+
+ void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const;
+
+ void eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const;
+
+ void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+
+ void emitPrologue(MachineFunction &MF) const;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+};
+
+} // end namespace llvm
+
+#endif
-//===-- PPC32TargetMachine.h - PowerPC/Darwin TargetMachine ---*- C++ -*-=//
+//===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file declares the PowerPC/Darwin specific subclass of TargetMachine.
+// This file declares the PowerPC specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
-#ifndef POWERPC_DARWIN_TARGETMACHINE_H
-#define POWERPC_DARWIN_TARGETMACHINE_H
+#ifndef POWERPC32_TARGETMACHINE_H
+#define POWERPC32_TARGETMACHINE_H
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/PassManager.h"
#include "PowerPCTargetMachine.h"
+#include "PPC32InstrInfo.h"
+#include "llvm/PassManager.h"
+#include <set>
namespace llvm {
+class GlobalValue;
class IntrinsicLowering;
class PPC32TargetMachine : public PowerPCTargetMachine {
+ PPC32InstrInfo InstrInfo;
+
public:
PPC32TargetMachine(const Module &M, IntrinsicLowering *IL);
+ virtual const PPC32InstrInfo *getInstrInfo() const { return &InstrInfo; }
+ virtual const MRegisterInfo *getRegisterInfo() const {
+ return &InstrInfo.getRegisterInfo();
+ }
- /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
- /// actually outputting the machine code and resolving things like the address
- /// of functions. This method should returns true if machine code emission is
- /// not supported.
- ///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE);
-
static unsigned getModuleMatchQuality(const Module &M);
+
+ bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE);
+
+ // Two shared sets between the instruction selector and the printer allow for
+ // correct linkage on Darwin
+ std::set<GlobalValue*> CalledFunctions;
+ std::set<GlobalValue*> AddressTaken;
};
} // end namespace llvm
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