drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag (v4)

Allows pinning of buffers in the non-CPU visible portion of
vram.

v2: incorporate Michel's comments.
v3: rebase on Michel's patch
v4: rebase on Michel's v2 patch

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 3dbbd65336d50ea723c7aa4579e25bde375875f6..8abee5fa93bd59c2bac81f181b2297f2f8c8f430 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -313,6 +313,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
        for (i = 0; i < bo->placement.num_placement; i++) {
                /* force to pin into visible video ram */
                if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
+                   !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
                    (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
                        bo->placements[i].lpfn =
                                bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;

diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index f755f20d2b5c2e51b008ff4efee77741b943e489..50d0fb41a3bf32cb2a796f3738adb10d79e3fb6c 100644 (file)
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -803,6 +803,8 @@ struct drm_radeon_gem_info {
 #define RADEON_GEM_GTT_WC              (1 << 2)
 /* BO is expected to be accessed by the CPU */
 #define RADEON_GEM_CPU_ACCESS          (1 << 3)
+/* CPU access is not expected to work for this BO */
+#define RADEON_GEM_NO_CPU_ACCESS       (1 << 4)
 
 struct drm_radeon_gem_create {
        uint64_t        size;