.platform_data = &tps65910_data,
},
#endif
+#if defined(CONFIG_HDMI_CAT66121)
+ {
+ .type = "cat66121_hdmi",
+ .addr = 0x4c,
+ .flags = 0,
+ .irq = RK30_PIN1_PB7,
+ },
+#endif
};
#endif
source "drivers/video/rockchip/hdmi/chips/rk2928/Kconfig"
endif
+config HDMI_CAT66121
+ bool "CAT66121 HDMI support"
+ help
+ Support cat66121 hdmi if you say y here
+
+if HDMI_CAT66121
+source "drivers/video/rockchip/hdmi/chips/cat66121/Kconfig"
+endif
+
config HDMI_RK610
bool "RK610 HDMI support"
depends on MFD_RK610
obj-$(CONFIG_HDMI_RK30) += rk30/
obj-$(CONFIG_HDMI_RK2928) += rk2928/
obj-$(CONFIG_HDMI_RK610) += rk610/
+obj-$(CONFIG_HDMI_CAT66121) += cat66121/
--- /dev/null
+obj-$(CONFIG_HDMI_CAT66121) += cat66121_hdmi.o \
+ cat66121_hdmi_hw.o \
+ hdmitx_sys.o \
+ hdmitx_hdcp.o \
+ hdmitx_input.o \
+ hdmitx_drv.o
+
--- /dev/null
+#include <linux/kernel.h>\r
+#include <linux/delay.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/interrupt.h>\r
+#include <mach/gpio.h>\r
+#include <mach/iomux.h>\r
+#include <linux/i2c.h>\r
+#include "cat66121_hdmi.h"\r
+\r
+struct cat66121_hdmi_pdata *cat66121_hdmi = NULL;\r
+struct hdmi *hdmi=NULL;\r
+\r
+extern struct rk_lcdc_device_driver * rk_get_lcdc_drv(char *name);\r
+extern void hdmi_register_display_sysfs(struct hdmi *hdmi, struct device *parent);\r
+extern void hdmi_unregister_display_sysfs(struct hdmi *hdmi);\r
+\r
+int cat66121_hdmi_register_hdcp_callbacks(void (*hdcp_cb)(void),\r
+ void (*hdcp_irq_cb)(int status),\r
+ int (*hdcp_power_on_cb)(void),\r
+ void (*hdcp_power_off_cb)(void))\r
+{\r
+ hdmi->hdcp_cb = hdcp_cb;\r
+ hdmi->hdcp_irq_cb = hdcp_irq_cb;\r
+ hdmi->hdcp_power_on_cb = hdcp_power_on_cb;\r
+ hdmi->hdcp_power_off_cb = hdcp_power_off_cb;\r
+ \r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+#ifdef CONFIG_HAS_EARLYSUSPEND\r
+static void hdmi_early_suspend(struct early_suspend *h)\r
+{\r
+ hdmi_dbg(hdmi->dev, "hdmi enter early suspend pwr %d state %d\n", hdmi->pwr_mode, hdmi->state);\r
+ flush_delayed_work(&hdmi->delay_work); \r
+ mutex_lock(&hdmi->enable_mutex);\r
+ hdmi->suspend = 1;\r
+ if(!hdmi->enable) {\r
+ mutex_unlock(&hdmi->enable_mutex);\r
+ return;\r
+ }\r
+ \r
+ #ifdef HDMI_USE_IRQ\r
+ if(hdmi->irq)\r
+ disable_irq(hdmi->irq);\r
+ #endif\r
+ \r
+ mutex_unlock(&hdmi->enable_mutex);\r
+ hdmi->command = HDMI_CONFIG_ENABLE;\r
+ init_completion(&hdmi->complete);\r
+ hdmi->wait = 1;\r
+ queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, 0);\r
+ wait_for_completion_interruptible_timeout(&hdmi->complete,\r
+ msecs_to_jiffies(5000));\r
+ flush_delayed_work(&hdmi->delay_work);\r
+ return;\r
+}\r
+\r
+static void hdmi_early_resume(struct early_suspend *h)\r
+{\r
+ hdmi_dbg(hdmi->dev, "hdmi exit early resume\n");\r
+ mutex_lock(&hdmi->enable_mutex);\r
+ \r
+ hdmi->suspend = 0;\r
+ #ifdef HDMI_USE_IRQ\r
+ if(hdmi->enable && hdmi->irq) {\r
+ enable_irq(hdmi->irq);\r
+ }\r
+ #else\r
+ queue_delayed_work(cat66121_hdmi->workqueue, &cat66121_hdmi->delay_work, 100);\r
+ #endif\r
+ queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10)); \r
+ mutex_unlock(&hdmi->enable_mutex);\r
+ return;\r
+}\r
+#endif\r
+\r
+static void cat66121_irq_work_func(struct work_struct *work)\r
+{\r
+ if(hdmi->suspend == 0) {\r
+ if(hdmi->enable == 1) {\r
+ cat66121_hdmi_interrupt();\r
+ if(hdmi->hdcp_irq_cb)\r
+ hdmi->hdcp_irq_cb(0);\r
+ }\r
+ #ifndef HDMI_USE_IRQ\r
+ queue_delayed_work(cat66121_hdmi->workqueue, &cat66121_hdmi->delay_work, 50);\r
+ #endif\r
+ }\r
+}\r
+\r
+#ifdef HDMI_USE_IRQ\r
+static irqreturn_t cat66121_irq(int irq, void *dev_id)\r
+{\r
+ printk(KERN_INFO "cat66121 irq triggered.\n");\r
+ schedule_work(&cat66121_hdmi->irq_work);\r
+ return IRQ_HANDLED;\r
+}\r
+#endif\r
+static int rk610_read_p0_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ return i2c_master_reg8_recv(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;\r
+}\r
+\r
+static int rk610_write_p0_reg(struct i2c_client *client, char reg, char *val)\r
+{\r
+ return i2c_master_reg8_send(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;\r
+}\r
+static ssize_t rk610_show_reg_attrs(struct device *dev,\r
+ struct device_attribute *attr,\r
+ char *buf)\r
+{\r
+\r
+ int i,size=0;\r
+ char val;\r
+ struct i2c_client *client=cat66121_hdmi->client;\r
+\r
+ for(i=0;i<256;i++)\r
+ {\r
+ rk610_read_p0_reg(client, i, &val);\r
+ if(i%16==0)\r
+ size += sprintf(buf+size,"\n>>>rk610_hdmi %x:",i);\r
+ size += sprintf(buf+size," %2x",val);\r
+ }\r
+\r
+ return size;\r
+}\r
+static ssize_t rk610_store_reg_attrs(struct device *dev,\r
+ struct device_attribute *attr,\r
+ const char *buf, size_t size)\r
+{\r
+ struct i2c_client *client=NULL;\r
+ static char val=0,reg=0;\r
+ client = cat66121_hdmi->client;\r
+ printk("/**********rk610 reg config******/");\r
+\r
+ sscanf(buf, "%x%x", &val,®);\r
+ printk("reg=%x val=%x\n",reg,val);\r
+ rk610_write_p0_reg(client, reg, &val);\r
+ printk("val=%x\n",val);\r
+ return size;\r
+}\r
+\r
+static struct device_attribute rk610_attrs[] = {\r
+ __ATTR(reg_ctl, 0777,rk610_show_reg_attrs,rk610_store_reg_attrs),\r
+};\r
+static int cat66121_hdmi_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)\r
+{\r
+ int rc = 0;\r
+ \r
+ cat66121_hdmi = kzalloc(sizeof(struct cat66121_hdmi_pdata), GFP_KERNEL);\r
+ if(!cat66121_hdmi)\r
+ {\r
+ dev_err(&client->dev, "no memory for state\n");\r
+ return -ENOMEM;\r
+ }\r
+ cat66121_hdmi->client = client;\r
+ i2c_set_clientdata(client, cat66121_hdmi);\r
+ \r
+ hdmi = kmalloc(sizeof(struct hdmi), GFP_KERNEL);\r
+ if(!hdmi)\r
+ {\r
+ dev_err(&client->dev, "cat66121 hdmi kmalloc fail!");\r
+ goto err_kzalloc_hdmi;\r
+ }\r
+ memset(hdmi, 0, sizeof(struct hdmi));\r
+ hdmi->dev = &client->dev;\r
+ \r
+ if(HDMI_SOURCE_DEFAULT == HDMI_SOURCE_LCDC0)\r
+ hdmi->lcdc = rk_get_lcdc_drv("lcdc0");\r
+ else\r
+ hdmi->lcdc = rk_get_lcdc_drv("lcdc1");\r
+ if(hdmi->lcdc == NULL)\r
+ {\r
+ dev_err(hdmi->dev, "can not connect to video source lcdc\n");\r
+ rc = -ENXIO;\r
+ goto err_request_lcdc;\r
+ }\r
+ hdmi->xscale = 100;\r
+ hdmi->yscale = 100;\r
+ hdmi->insert = cat66121_hdmi_sys_insert;\r
+ hdmi->remove = cat66121_hdmi_sys_remove;\r
+ hdmi->control_output = cat66121_hdmi_sys_enalbe_output;\r
+ hdmi->config_video = cat66121_hdmi_sys_config_video;\r
+ hdmi->config_audio = cat66121_hdmi_sys_config_audio;\r
+ hdmi->detect_hotplug = cat66121_hdmi_sys_detect_hpd;\r
+ hdmi->read_edid = cat66121_hdmi_sys_read_edid;\r
+ hdmi_sys_init();\r
+ \r
+ hdmi->workqueue = create_singlethread_workqueue("hdmi");\r
+ INIT_DELAYED_WORK(&(hdmi->delay_work), hdmi_work);\r
+ \r
+ #ifdef CONFIG_HAS_EARLYSUSPEND\r
+ hdmi->early_suspend.suspend = hdmi_early_suspend;\r
+ hdmi->early_suspend.resume = hdmi_early_resume;\r
+ hdmi->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 10;\r
+ register_early_suspend(&hdmi->early_suspend);\r
+ #endif\r
+ \r
+ hdmi_register_display_sysfs(hdmi, NULL);\r
+ #ifdef CONFIG_SWITCH\r
+ hdmi->switch_hdmi.name="hdmi";\r
+ switch_dev_register(&(hdmi->switch_hdmi));\r
+ #endif\r
+ \r
+ spin_lock_init(&hdmi->irq_lock);\r
+ mutex_init(&hdmi->enable_mutex);\r
+ \r
+ cat66121_hdmi_sys_init();\r
+ rc = gpio_request(client->irq, "cat66121 rst");\r
+ if (rc != 0) {\r
+ gpio_free(client->irq);\r
+ printk("goodix power error\n");\r
+ return -EIO;\r
+ }\r
+ gpio_direction_output(client->irq, GPIO_HIGH);\r
+ gpio_set_value(client->irq, GPIO_HIGH);\r
+ msleep(10);\r
+ gpio_set_value(client->irq, GPIO_LOW);\r
+ msleep(200);\r
+ gpio_set_value(client->irq, GPIO_HIGH);\r
+#ifdef HDMI_USE_IRQ\r
+ if(client->irq != INVALID_GPIO) {\r
+ INIT_WORK(&cat66121_hdmi->irq_work, cat66121_irq_work_func);\r
+ schedule_work(&cat66121_hdmi->irq_work);\r
+ if((rc = gpio_request(client->irq, "hdmi gpio")) < 0)\r
+ {\r
+ dev_err(&client->dev, "fail to request gpio %d\n", client->irq);\r
+ goto err_request_lcdc;\r
+ }\r
+ hdmi->irq = gpio_to_irq(client->irq);\r
+ cat66121_hdmi->gpio = client->irq;\r
+ gpio_pull_updown(client->irq, GPIOPullUp);\r
+ gpio_direction_input(client->irq);\r
+ if((rc = request_irq(hdmi->irq, cat66121_irq, IRQF_TRIGGER_RISING, NULL, hdmi)) < 0)\r
+ {\r
+ dev_err(&client->dev, "fail to request hdmi irq\n");\r
+ goto err_request_irq;\r
+ }\r
+ }\r
+ else\r
+#else\r
+ {\r
+ cat66121_hdmi->workqueue = create_singlethread_workqueue("cat66121 irq");\r
+ INIT_DELAYED_WORK(&(cat66121_hdmi->delay_work), cat66121_irq_work_func);\r
+ cat66121_irq_work_func(NULL);\r
+ }\r
+#endif\r
+\r
+ device_create_file(&(client->dev), &rk610_attrs[0]);\r
+ dev_info(&client->dev, "cat66121 hdmi i2c probe ok\n");\r
+ \r
+ return 0;\r
+ \r
+err_request_irq:\r
+ gpio_free(client->irq);\r
+err_request_lcdc:\r
+ kfree(hdmi);\r
+ hdmi = NULL;\r
+err_kzalloc_hdmi:\r
+ kfree(cat66121_hdmi);\r
+ cat66121_hdmi = NULL;\r
+ dev_err(&client->dev, "cat66121 hdmi probe error\n");\r
+ return rc;\r
+\r
+}\r
+\r
+static int __devexit cat66121_hdmi_i2c_remove(struct i2c_client *client)\r
+{ \r
+ hdmi_dbg(hdmi->dev, "%s\n", __func__);\r
+ if(hdmi) {\r
+ mutex_lock(&hdmi->enable_mutex);\r
+ if(!hdmi->suspend && hdmi->enable && hdmi->irq)\r
+ disable_irq(hdmi->irq);\r
+ mutex_unlock(&hdmi->enable_mutex);\r
+ if(hdmi->irq)\r
+ free_irq(hdmi->irq, NULL);\r
+ flush_workqueue(hdmi->workqueue);\r
+ destroy_workqueue(hdmi->workqueue);\r
+ #ifdef CONFIG_SWITCH\r
+ switch_dev_unregister(&(hdmi->switch_hdmi));\r
+ #endif\r
+ hdmi_unregister_display_sysfs(hdmi);\r
+ #ifdef CONFIG_HAS_EARLYSUSPEND\r
+ unregister_early_suspend(&hdmi->early_suspend);\r
+ #endif\r
+ fb_destroy_modelist(&hdmi->edid.modelist);\r
+ if(hdmi->edid.audio)\r
+ kfree(hdmi->edid.audio);\r
+ if(hdmi->edid.specs)\r
+ {\r
+ if(hdmi->edid.specs->modedb)\r
+ kfree(hdmi->edid.specs->modedb);\r
+ kfree(hdmi->edid.specs);\r
+ }\r
+ kfree(hdmi);\r
+ hdmi = NULL;\r
+ }\r
+ return 0;\r
+}\r
+\r
+static void cat66121_hdmi_i2c_shutdown(struct i2c_client *client)\r
+{\r
+ if(hdmi) {\r
+ #ifdef CONFIG_HAS_EARLYSUSPEND\r
+ unregister_early_suspend(&hdmi->early_suspend);\r
+ #endif\r
+ }\r
+ printk(KERN_INFO "cat66121 hdmi shut down.\n");\r
+}\r
+\r
+static const struct i2c_device_id cat66121_hdmi_id[] = {\r
+ { "cat66121_hdmi", 0 },\r
+ { }\r
+};\r
+\r
+static struct i2c_driver cat66121_hdmi_i2c_driver = {\r
+ .driver = {\r
+ .name = "cat66121_hdmi",\r
+ .owner = THIS_MODULE,\r
+ },\r
+ .probe = cat66121_hdmi_i2c_probe,\r
+ .remove = cat66121_hdmi_i2c_remove,\r
+ .shutdown = cat66121_hdmi_i2c_shutdown,\r
+ .id_table = cat66121_hdmi_id,\r
+};\r
+\r
+static int __init cat66121_hdmi_init(void)\r
+{\r
+ return i2c_add_driver(&cat66121_hdmi_i2c_driver);\r
+}\r
+\r
+static void __exit cat66121_hdmi_exit(void)\r
+{\r
+ i2c_del_driver(&cat66121_hdmi_i2c_driver);\r
+}\r
+\r
+module_init(cat66121_hdmi_init);\r
+//fs_initcall(cat66121_init);\r
+module_exit(cat66121_hdmi_exit);\r
--- /dev/null
+#ifndef __cat66121_HDMI_H__\r
+#define __cat66121_HDMI_H__\r
+#include "../../rk_hdmi.h"\r
+\r
+#define HDMI_SOURCE_DEFAULT HDMI_SOURCE_LCDC0\r
+//#define HDMI_USE_IRQ\r
+\r
+struct cat66121_hdmi_pdata {\r
+ int gpio;\r
+ struct i2c_client *client;\r
+ struct delayed_work delay_work;\r
+ #ifdef HDMI_USE_IRQ\r
+ struct work_struct irq_work;\r
+ #else\r
+ struct workqueue_struct *workqueue;\r
+ #endif\r
+};\r
+\r
+extern struct cat66121_hdmi_pdata *cat66121_hdmi;\r
+\r
+extern int cat66121_hdmi_sys_init(void);\r
+extern void cat66121_hdmi_interrupt(void);\r
+extern int cat66121_hdmi_sys_detect_hpd(void);\r
+extern int cat66121_hdmi_sys_insert(void);\r
+extern int cat66121_hdmi_sys_remove(void);\r
+extern int cat66121_hdmi_sys_read_edid(int block, unsigned char *buff);\r
+extern int cat66121_hdmi_sys_config_video(struct hdmi_video_para *vpara);\r
+extern int cat66121_hdmi_sys_config_audio(struct hdmi_audio *audio);\r
+extern void cat66121_hdmi_sys_enalbe_output(int enable);\r
+extern int cat66121_hdmi_register_hdcp_callbacks(void (*hdcp_cb)(void),\r
+ void (*hdcp_irq_cb)(int status),\r
+ int (*hdcp_power_on_cb)(void),\r
+ void (*hdcp_power_off_cb)(void));\r
+#endif\r
--- /dev/null
+#include <linux/delay.h>\r
+#include "cat66121_hdmi.h"\r
+#include "cat66121_hdmi_hw.h"\r
+#include <asm/atomic.h>\r
+#include <mach/io.h>\r
+#include <mach/gpio.h>\r
+#include <mach/iomux.h>\r
+\r
+#define HDMITX_INPUT_SIGNAL_TYPE 0 // for default(Sync Sep Mode)\r
+#define INPUT_SPDIF_ENABLE 0\r
+extern int CAT66121_Interrupt_Process(void);\r
+/*******************************\r
+ * Global Data\r
+ ******************************/\r
+static _XDATA AVI_InfoFrame AviInfo;\r
+static _XDATA Audio_InfoFrame AudioInfo;\r
+static unsigned long VideoPixelClock;\r
+static unsigned int pixelrep;\r
+\r
+/* I2C read/write funcs */\r
+BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr)\r
+{\r
+ struct i2c_msg msgs[2];\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[1];\r
+\r
+ buf[0] = RegAddr;\r
+\r
+ /* Write device addr fisrt */\r
+ msgs[0].addr = cat66121_hdmi->client->addr;\r
+ msgs[0].flags = !I2C_M_RD;\r
+ msgs[0].len = 1;\r
+ msgs[0].buf = &buf[0];\r
+ msgs[0].scl_rate= 100*1000;\r
+ /* Then, begin to read data */\r
+ msgs[1].addr = cat66121_hdmi->client->addr;\r
+ msgs[1].flags = I2C_M_RD;\r
+ msgs[1].len = 1;\r
+ msgs[1].buf = &buf[0];\r
+ msgs[1].scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);\r
+ if(ret != 2)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ //ErrorF("Reg%02xH: 0x%02x\n", RegAddr, buf[0]);\r
+ return buf[0];\r
+}\r
+\r
+SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr, BYTE data)\r
+{\r
+ struct i2c_msg msg;\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[2];\r
+\r
+ buf[0] = RegAddr;\r
+ buf[1] = data;\r
+\r
+ msg.addr = cat66121_hdmi->client->addr;\r
+ msg.flags = !I2C_M_RD;\r
+ msg.len = 2;\r
+ msg.buf = buf; \r
+ msg.scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);\r
+ if(ret != 1)\r
+ printk("I2C transfer Error!\n");\r
+\r
+ return ret;\r
+}\r
+\r
+SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)\r
+{\r
+ struct i2c_msg msgs[2];\r
+ SYS_STATUS ret = -1;\r
+\r
+ pData[0] = RegAddr;\r
+\r
+ msgs[0].addr = cat66121_hdmi->client->addr;\r
+ msgs[0].flags = !I2C_M_RD;\r
+ msgs[0].len = 1;\r
+ msgs[0].buf = &pData[0];\r
+ msgs[0].scl_rate= 100*1000;\r
+\r
+ msgs[1].addr = cat66121_hdmi->client->addr;\r
+ msgs[1].flags = I2C_M_RD;\r
+ msgs[1].len = N;\r
+ msgs[1].buf = pData;\r
+ msgs[1].scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);\r
+ if(ret != 2)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ return ret;\r
+}\r
+\r
+SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)\r
+{\r
+ struct i2c_msg msg;\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[N + 1];\r
+\r
+ buf[0] = RegAddr;\r
+ memcpy(&buf[1], pData, N);\r
+\r
+ msg.addr = cat66121_hdmi->client->addr;\r
+ msg.flags = !I2C_M_RD;\r
+ msg.len = N + 1;\r
+ msg.buf = buf; // gModify.Exp."Include RegAddr"\r
+ msg.scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);\r
+ if(ret != 1)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ return ret;\r
+}\r
+SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value)\r
+{\r
+ BYTE Temp;\r
+ if( Mask != 0xFF )\r
+ {\r
+ Temp=HDMITX_ReadI2C_Byte(Reg);\r
+ Temp&=(~Mask);\r
+ Temp|=Value&Mask;\r
+ }\r
+ else\r
+ {\r
+ Temp=Value;\r
+ }\r
+ return HDMITX_WriteI2C_Byte(Reg,Temp);\r
+}\r
+int cat66121_hdmi_sys_init(void)\r
+{\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+ rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME, GPIO0C_GPIO0C1);\r
+ if (gpio_request(RK30_PIN0_PC1, NULL)) {\r
+ printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);\r
+ return -1;\r
+ }\r
+ gpio_direction_output(RK30_PIN0_PC1, GPIO_LOW);\r
+ gpio_set_value(RK30_PIN0_PC1, GPIO_LOW);\r
+ msleep(200);\r
+ gpio_set_value(RK30_PIN0_PC1, GPIO_HIGH);\r
+ msleep(200);\r
+\r
+ mdelay(5);\r
+ VideoPixelClock = 0;\r
+ pixelrep = 0;\r
+ InitHDMITX_Variable();\r
+ InitHDMITX();\r
+ msleep(100);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+void cat66121_hdmi_interrupt()\r
+{\r
+ char interrupt = 0;\r
+\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+ if(hdmi->state == HDMI_SLEEP)\r
+ hdmi->state = WAIT_HOTPLUG;\r
+ queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10)); \r
+}\r
+\r
+int cat66121_hdmi_sys_detect_hpd(void)\r
+{\r
+ char hdmi_status = 0;\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+ // BYTE sysstat;\r
+\r
+ //sysstat = HDMITX_ReadI2C_Byte(REG_SYS_STATUS) ; \r
+ //*hpdstatus = ((sysstat & B_HPDETECT) == B_HPDETECT)?TRUE:FALSE ;\r
+ hdmi_status = HDMITX_DevLoopProc();\r
+;\r
+ return HDMI_HPD_ACTIVED;\r
+ if(hdmi_status)\r
+ return HDMI_HPD_ACTIVED;\r
+ else\r
+ return HDMI_HPD_REMOVED;\r
+}\r
+\r
+int cat66121_hdmi_sys_read_edid(int block, unsigned char *buff)\r
+{\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+ return (getHDMITX_EDIDBlock(block, buff) == TRUE)?HDMI_ERROR_SUCESS:HDMI_ERROR_FALSE;\r
+}\r
+\r
+static void cat66121_sys_config_avi(int VIC, int bOutputColorMode, int aspec, int Colorimetry, int pixelrep)\r
+{\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+// AVI_InfoFrame AviInfo;\r
+\r
+}\r
+\r
+int cat66121_hdmi_sys_config_video(struct hdmi_video_para *vpara)\r
+{\r
+ printk( "[%s]\n", __FUNCTION__);\r
+ printk( "[%s]\n", __FUNCTION__);\r
+ HDMITX_ChangeDisplayOption(vpara->vic,HDMI_RGB444) ;\r
+\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+static void cat66121_hdmi_config_aai(void)\r
+{\r
+ printk( "[%s]\n", __FUNCTION__);\r
+}\r
+\r
+int cat66121_hdmi_sys_config_audio(struct hdmi_audio *audio)\r
+{\r
+ printk( "[%s]\n", __FUNCTION__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+void cat66121_hdmi_sys_enalbe_output(int enable)\r
+{\r
+ \r
+ printk( "[%s]\n", __FUNCTION__);\r
+}\r
+\r
+int cat66121_hdmi_sys_insert(void)\r
+{\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+ printk( "[%s]\n", __FUNCTION__);\r
+ return 0;\r
+}\r
+\r
+int cat66121_hdmi_sys_remove(void)\r
+{\r
+ hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);\r
+// printk( "[%s]\n", __FUNCTION__);\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+#ifndef _CAT6611_HDMI_HW_H
+#define _CAT6611_HDMI_HW_H
+
+#include "typedef.h"
+#include "hdmitx_drv.h"
+#include "hdmitx_sys.h"
+#define CAT6611_SCL_RATE 100 * 1000
+#define I2S 0
+#define SPDIF 1
+
+#ifndef I2S_FORMAT
+#define I2S_FORMAT 0x01 // 32bit audio
+#endif
+
+#ifndef INPUT_SAMPLE_FREQ
+ #define INPUT_SAMPLE_FREQ AUDFS_48KHz
+#endif //INPUT_SAMPLE_FREQ
+
+#ifndef INPUT_SAMPLE_FREQ_HZ
+ #define INPUT_SAMPLE_FREQ_HZ 48000L
+#endif //INPUT_SAMPLE_FREQ_HZ
+
+#ifndef OUTPUT_CHANNEL
+ #define OUTPUT_CHANNEL 2
+#endif //OUTPUT_CHANNEL
+
+#ifndef CNOFIG_INPUT_AUDIO_TYPE
+ #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM
+ // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM
+ // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR
+#endif //CNOFIG_INPUT_AUDIO_TYPE
+
+#ifndef CONFIG_INPUT_AUDIO_SPDIF
+ #define CONFIG_INPUT_AUDIO_SPDIF I2S
+ // #define CONFIG_INPUT_AUDIO_SPDIF SPDIF
+#endif //CONFIG_INPUT_AUDIO_SPDIF
+
+#ifndef INPUT_SIGNAL_TYPE
+#define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// Internal Data Type
+////////////////////////////////////////////////////////////////////////////////
+
+typedef enum tagHDMI_Video_Type {
+ HDMI_Unkown = 0 ,
+ HDMI_640x480p60 = 1 ,
+ HDMI_480p60,
+ HDMI_480p60_16x9,
+ HDMI_720p60,
+ HDMI_1080i60,
+ HDMI_480i60,
+ HDMI_480i60_16x9,
+ HDMI_1080p60 = 16,
+ HDMI_576p50,
+ HDMI_576p50_16x9,
+ HDMI_720p50,
+ HDMI_1080i50,
+ HDMI_576i50,
+ HDMI_576i50_16x9,
+ HDMI_1080p50 = 31,
+ HDMI_1080p24,
+ HDMI_1080p25,
+ HDMI_1080p30,
+ HDMI_720p30 = 61,
+} HDMI_Video_Type ;
+
+typedef enum tagHDMI_Aspec {
+ HDMI_4x3 ,
+ HDMI_16x9
+} HDMI_Aspec;
+
+typedef enum tagHDMI_OutputColorMode {
+ HDMI_RGB444,
+ HDMI_YUV444,
+ HDMI_YUV422
+} HDMI_OutputColorMode ;
+
+typedef enum tagHDMI_Colorimetry {
+ HDMI_ITU601,
+ HDMI_ITU709
+} HDMI_Colorimetry ;
+
+struct VideoTiming {
+ ULONG VideoPixelClock ;
+ BYTE VIC ;
+ BYTE pixelrep ;
+ BYTE outputVideoMode ;
+} ;
+
+
+
+typedef enum _TXVideo_State_Type {
+ TXVSTATE_Unplug = 0,
+ TXVSTATE_HPD,
+ TXVSTATE_WaitForMode,
+ TXVSTATE_WaitForVStable,
+ TXVSTATE_VideoInit,
+ TXVSTATE_VideoSetup,
+ TXVSTATE_VideoOn,
+ TXVSTATE_Reserved
+} TXVideo_State_Type ;
+
+
+typedef enum _TXAudio_State_Type {
+ TXASTATE_AudioOff = 0,
+ TXASTATE_AudioPrepare,
+ TXASTATE_AudioOn,
+ TXASTATE_AudioFIFOFail,
+ TXASTATE_Reserved
+} TXAudio_State_Type ;
+/////////////////////////////////////////
+// RX Capability.
+/////////////////////////////////////////
+typedef struct {
+ BYTE b16bit:1 ;
+ BYTE b20bit:1 ;
+ BYTE b24bit:1 ;
+ BYTE Rsrv:5 ;
+} LPCM_BitWidth ;
+
+typedef enum {
+ AUD_RESERVED_0 = 0 ,
+ AUD_LPCM,
+ AUD_AC3,
+ AUD_MPEG1,
+ AUD_MP3,
+ AUD_MPEG2,
+ AUD_AAC,
+ AUD_DTS,
+ AUD_ATRAC,
+ AUD_ONE_BIT_AUDIO,
+ AUD_DOLBY_DIGITAL_PLUS,
+ AUD_DTS_HD,
+ AUD_MAT_MLP,
+ AUD_DST,
+ AUD_WMA_PRO,
+ AUD_RESERVED_15
+} AUDIO_FORMAT_CODE ;
+
+typedef union {
+ struct {
+ BYTE channel:3 ;
+ BYTE AudioFormatCode:4 ;
+ BYTE Rsrv1:1 ;
+
+ BYTE b32KHz:1 ;
+ BYTE b44_1KHz:1 ;
+ BYTE b48KHz:1 ;
+ BYTE b88_2KHz:1 ;
+ BYTE b96KHz:1 ;
+ BYTE b176_4KHz:1 ;
+ BYTE b192KHz:1 ;
+ BYTE Rsrv2:1 ;
+ BYTE ucCode ;
+ } s ;
+ BYTE uc[3] ;
+} AUDDESCRIPTOR ;
+
+typedef union {
+ struct {
+ BYTE FL_FR:1 ;
+ BYTE LFE:1 ;
+ BYTE FC:1 ;
+ BYTE RL_RR:1 ;
+ BYTE RC:1 ;
+ BYTE FLC_FRC:1 ;
+ BYTE RLC_RRC:1 ;
+ BYTE Reserve:1 ;
+ BYTE Unuse[2] ;
+ } s ;
+ BYTE uc[3] ;
+} SPK_ALLOC ;
+
+#define CEA_SUPPORT_UNDERSCAN (1<<7)
+#define CEA_SUPPORT_AUDIO (1<<6)
+#define CEA_SUPPORT_YUV444 (1<<5)
+#define CEA_SUPPORT_YUV422 (1<<4)
+#define CEA_NATIVE_MASK 0xF
+
+
+#define HDMI_DC_SUPPORT_AI (1<<7)
+#define HDMI_DC_SUPPORT_48 (1<<6)
+#define HDMI_DC_SUPPORT_36 (1<<5)
+#define HDMI_DC_SUPPORT_30 (1<<4)
+#define HDMI_DC_SUPPORT_Y444 (1<<3)
+#define HDMI_DC_SUPPORT_DVI_DUAL 1
+
+typedef union _tag_DCSUPPORT {
+ struct {
+ BYTE DVI_Dual:1 ;
+ BYTE Rsvd:2 ;
+ BYTE DC_Y444:1 ;
+ BYTE DC_30Bit:1 ;
+ BYTE DC_36Bit:1 ;
+ BYTE DC_48Bit:1 ;
+ BYTE SUPPORT_AI:1 ;
+ } info ;
+ BYTE uc ;
+} DCSUPPORT ;
+
+typedef union _LATENCY_SUPPORT{
+ struct {
+ BYTE Rsvd:6 ;
+ BYTE I_Latency_Present:1 ;
+ BYTE Latency_Present:1 ;
+ } info ;
+ BYTE uc ;
+} LATENCY_SUPPORT ;
+
+#define HDMI_IEEEOUI 0x0c03
+#define MAX_VODMODE_COUNT 32
+#define MAX_AUDDES_COUNT 4
+
+typedef struct _RX_CAP{
+ BYTE VideoMode ;
+ BYTE NativeVDOMode ;
+ BYTE VDOMode[8] ;
+ BYTE AUDDesCount ;
+ AUDDESCRIPTOR AUDDes[MAX_AUDDES_COUNT] ;
+ BYTE PA[2] ;
+ ULONG IEEEOUI ;
+ DCSUPPORT dc ;
+ BYTE MaxTMDSClock ;
+ LATENCY_SUPPORT lsupport ;
+ SPK_ALLOC SpeakerAllocBlk ;
+ BYTE ValidCEA:1 ;
+ BYTE ValidHDMI:1 ;
+ BYTE Valid3D:1 ;
+} RX_CAP ;
+
+///////////////////////////////////////////////////////////////////////
+// Output Mode Type
+///////////////////////////////////////////////////////////////////////
+
+#define RES_ASPEC_4x3 0
+#define RES_ASPEC_16x9 1
+#define F_MODE_REPT_NO 0
+#define F_MODE_REPT_TWICE 1
+#define F_MODE_REPT_QUATRO 3
+#define F_MODE_CSC_ITU601 0
+#define F_MODE_CSC_ITU709 1
+
+BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);
+SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);
+SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
+SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
+SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);
+
+void InitHDMITX_Variable();
+void HDMITX_ChangeDisplayOption(HDMI_Video_Type VideoMode, HDMI_OutputColorMode OutputColorMode);
+void HDMITX_SetOutput();
+int HDMITX_DevLoopProc();
+void ConfigfHdmiVendorSpecificInfoFrame(BYTE _3D_Stru);
+void HDMITX_ChangeAudioOption(BYTE Option, BYTE channelNum, BYTE AudioFs);
+void HDMITX_SetAudioOutput();
+void HDMITX_ChangeColorDepth(BYTE colorDepth);
+
+#endif
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file >cat66121_sys.c<\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2009/08/24\r
+// @fileversion: cat66121_SAMPLEINTERFACE_1.12\r
+//******************************************/\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// This is the sample program for cat66121 driver usage.\r
+///////////////////////////////////////////////////////////////////////////////\r
+\r
+#include "hdmitx.h"\r
+#include "hdmitx_sys.h"\r
+#include "cat66121_hdmi.h"\r
+\r
+#if 0\r
+BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);\r
+SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);\r
+SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);\r
+SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);\r
+SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);\r
+#endif\r
+/* I2C read/write funcs */\r
+BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr)\r
+{\r
+ struct i2c_msg msgs[2];\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[1];\r
+\r
+ buf[0] = RegAddr;\r
+\r
+ /* Write device addr fisrt */\r
+ msgs[0].addr = cat66121_hdmi->client->addr;\r
+ msgs[0].flags = !I2C_M_RD;\r
+ msgs[0].len = 1;\r
+ msgs[0].buf = &buf[0];\r
+ msgs[0].scl_rate= 100*1000;\r
+ /* Then, begin to read data */\r
+ msgs[1].addr = cat66121_hdmi->client->addr;\r
+ msgs[1].flags = I2C_M_RD;\r
+ msgs[1].len = 1;\r
+ msgs[1].buf = &buf[0];\r
+ msgs[1].scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);\r
+ if(ret != 2)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ //ErrorF("Reg%02xH: 0x%02x\n", RegAddr, buf[0]);\r
+ return buf[0];\r
+}\r
+\r
+SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr, BYTE data)\r
+{\r
+ struct i2c_msg msg;\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[2];\r
+\r
+ buf[0] = RegAddr;\r
+ buf[1] = data;\r
+\r
+ msg.addr = cat66121_hdmi->client->addr;\r
+ msg.flags = !I2C_M_RD;\r
+ msg.len = 2;\r
+ msg.buf = buf; \r
+ msg.scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);\r
+ if(ret != 1)\r
+ printk("I2C transfer Error!\n");\r
+\r
+ return ret;\r
+}\r
+\r
+SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)\r
+{\r
+ struct i2c_msg msgs[2];\r
+ SYS_STATUS ret = -1;\r
+\r
+ pData[0] = RegAddr;\r
+\r
+ msgs[0].addr = cat66121_hdmi->client->addr;\r
+ msgs[0].flags = !I2C_M_RD;\r
+ msgs[0].len = 1;\r
+ msgs[0].buf = &pData[0];\r
+ msgs[0].scl_rate= 100*1000;\r
+\r
+ msgs[1].addr = cat66121_hdmi->client->addr;\r
+ msgs[1].flags = I2C_M_RD;\r
+ msgs[1].len = N;\r
+ msgs[1].buf = pData;\r
+ msgs[1].scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);\r
+ if(ret != 2)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ return ret;\r
+}\r
+\r
+SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)\r
+{\r
+ struct i2c_msg msg;\r
+ SYS_STATUS ret = -1;\r
+ BYTE buf[N + 1];\r
+\r
+ buf[0] = RegAddr;\r
+ memcpy(&buf[1], pData, N);\r
+\r
+ msg.addr = cat66121_hdmi->client->addr;\r
+ msg.flags = !I2C_M_RD;\r
+ msg.len = N + 1;\r
+ msg.buf = buf; // gModify.Exp."Include RegAddr"\r
+ msg.scl_rate= 100*1000;\r
+ \r
+ ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);\r
+ if(ret != 1)\r
+ printk("I2C transfer Error! ret = %d\n", ret);\r
+\r
+ return ret;\r
+}\r
+static int cat66121_hdmi_i2c_read_reg(char reg, char *val)\r
+{\r
+ if(i2c_master_reg8_recv(cat66121_hdmi->client, reg, val, 1, 100*1000) > 0)\r
+ return 0;\r
+ else {\r
+ printk("[%s] reg %02x error\n", __FUNCTION__, reg);\r
+ return -EINVAL;\r
+ }\r
+}\r
+/*******************************\r
+ * Global Data\r
+ ******************************/\r
+\r
+/*******************************\r
+ * Functions\r
+ ******************************/\r
+int cat66121_detect_device(void)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return 0;\r
+}\r
+\r
+int cat66121_sys_init(struct hdmi *hdmi)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ InitHDMITX_Variable();\r
+ InitHDMITX();\r
+ HDMITX_ChangeDisplayOption(HDMI_720p60,HDMI_RGB444) ;\r
+ HDMITX_DevLoopProc();\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_unplug(struct hdmi *hdmi)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_detect_hpd(struct hdmi *hdmi, int *hpdstatus)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ *hpdstatus = TRUE;\r
+ \r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_detect_sink(struct hdmi *hdmi, int *sink_status)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ *sink_status = TRUE;\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+static void cat66121_sys_config_avi(int VIC, int bOutputColorMode, int aspec, int Colorimetry, int pixelrep)\r
+{\r
+}\r
+\r
+int cat66121_sys_config_video(struct hdmi *hdmi, int vic, int input_color, int output_color)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ HDMITX_DevLoopProc();\r
+ return HDMI_ERROR_SUCESS ;\r
+}\r
+\r
+static void cat66121_sys_config_aai(void)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+}\r
+\r
+int cat66121_sys_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_config_hdcp(struct hdmi *hdmi, int enable)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
+\r
+int cat66121_sys_enalbe_output(struct hdmi *hdmi, int enable)\r
+{\r
+ printk(">>>%s \n",__func__);\r
+ return HDMI_ERROR_SUCESS;\r
+}\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file >cat66121_sys.h<\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2009/08/24\r
+// @fileversion: cat66121_SAMPLEINTERFACE_1.12\r
+//******************************************/\r
+\r
+#ifndef _CAT66121_SYS_H_\r
+#define _CAT66121_SYS_H_\r
+////////////////////////////////////////////////////////////////////////////////\r
+// Internal Data Type\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+typedef enum tagHDMI_Video_Type {\r
+ HDMI_Unkown = 0 ,\r
+ HDMI_640x480p60 = 1 ,\r
+ HDMI_480p60,\r
+ HDMI_480p60_16x9,\r
+ HDMI_720p60,\r
+ HDMI_1080i60,\r
+ HDMI_480i60,\r
+ HDMI_480i60_16x9,\r
+ HDMI_1080p60 = 16,\r
+ HDMI_576p50,\r
+ HDMI_576p50_16x9,\r
+ HDMI_720p50,\r
+ HDMI_1080i50,\r
+ HDMI_576i50,\r
+ HDMI_576i50_16x9,\r
+ HDMI_1080p50 = 31,\r
+ HDMI_1080p24,\r
+ HDMI_1080p25,\r
+ HDMI_1080p30,\r
+} HDMI_Video_Type ;\r
+\r
+typedef enum tagHDMI_Aspec {\r
+ HDMI_4x3 ,\r
+ HDMI_16x9\r
+} HDMI_Aspec;\r
+\r
+typedef enum tagHDMI_OutputColorMode {\r
+ HDMI_RGB444,\r
+ HDMI_YUV444,\r
+ HDMI_YUV422\r
+} HDMI_OutputColorMode ;\r
+\r
+typedef enum tagHDMI_Colorimetry {\r
+ HDMI_ITU601,\r
+ HDMI_ITU709\r
+} HDMI_Colorimetry ;\r
+\r
+typedef enum tagMODE_ID{ \r
+ CEA_640x480p60, \r
+ CEA_720x480p60, \r
+ CEA_1280x720p60, \r
+ CEA_1920x1080i60, \r
+ CEA_720x480i60, \r
+ CEA_720x240p60, \r
+ CEA_1440x480i60, \r
+ CEA_1440x240p60, \r
+ CEA_2880x480i60, \r
+ CEA_2880x240p60, \r
+ CEA_1440x480p60, \r
+ CEA_1920x1080p60,\r
+ CEA_720x576p50, \r
+ CEA_1280x720p50, \r
+ CEA_1920x1080i50, \r
+ CEA_720x576i50, \r
+ CEA_1440x576i50, \r
+ CEA_720x288p50, \r
+ CEA_1440x288p50,\r
+ CEA_2880x576i50,\r
+ CEA_2880x288p50,\r
+ CEA_1440x576p50,\r
+ CEA_1920x1080p50,\r
+ CEA_1920x1080p24,\r
+ CEA_1920x1080p25,\r
+ CEA_1920x1080p30,\r
+ VESA_640x350p85,\r
+ VESA_640x400p85,\r
+ VESA_720x400p85,\r
+ VESA_640x480p60,\r
+ VESA_640x480p72,\r
+ VESA_640x480p75,\r
+ VESA_640x480p85,\r
+ VESA_800x600p56,\r
+ VESA_800x600p60,\r
+ VESA_800x600p72,\r
+ VESA_800x600p75,\r
+ VESA_800X600p85,\r
+ VESA_840X480p60,\r
+ VESA_1024x768p60,\r
+ VESA_1024x768p70,\r
+ VESA_1024x768p75,\r
+ VESA_1024x768p85,\r
+ VESA_1152x864p75,\r
+ VESA_1280x768p60R,\r
+ VESA_1280x768p60,\r
+ VESA_1280x768p75,\r
+ VESA_1280x768p85,\r
+ VESA_1280x960p60,\r
+ VESA_1280x960p85,\r
+ VESA_1280x1024p60,\r
+ VESA_1280x1024p75,\r
+ VESA_1280X1024p85,\r
+ VESA_1360X768p60,\r
+ VESA_1400x768p60R,\r
+ VESA_1400x768p60,\r
+ VESA_1400x1050p75,\r
+ VESA_1400x1050p85,\r
+ VESA_1440x900p60R,\r
+ VESA_1440x900p60,\r
+ VESA_1440x900p75,\r
+ VESA_1440x900p85,\r
+ VESA_1600x1200p60,\r
+ VESA_1600x1200p65,\r
+ VESA_1600x1200p70,\r
+ VESA_1600x1200p75,\r
+ VESA_1600x1200p85,\r
+ VESA_1680x1050p60R,\r
+ VESA_1680x1050p60,\r
+ VESA_1680x1050p75,\r
+ VESA_1680x1050p85,\r
+ VESA_1792x1344p60,\r
+ VESA_1792x1344p75,\r
+ VESA_1856x1392p60,\r
+ VESA_1856x1392p75,\r
+ VESA_1920x1200p60R,\r
+ VESA_1920x1200p60,\r
+ VESA_1920x1200p75,\r
+ VESA_1920x1200p85,\r
+ VESA_1920x1440p60,\r
+ VESA_1920x1440p75,\r
+ UNKNOWN_MODE \r
+} MODE_ID;\r
+///////////////////////////////////////////////////////////////////////\r
+// Output Mode Type\r
+///////////////////////////////////////////////////////////////////////\r
+\r
+#define RES_ASPEC_4x3 0\r
+#define RES_ASPEC_16x9 1\r
+#define F_MODE_REPT_NO 0\r
+#define F_MODE_REPT_TWICE 1\r
+#define F_MODE_REPT_QUATRO 3\r
+#define F_MODE_CSC_ITU601 0\r
+#define F_MODE_CSC_ITU709 1\r
+\r
+/* Follow prototypes need accomplish by ourself */\r
+int cat66121_detect_device(void);\r
+int cat66121_sys_init(struct hdmi *hdmi);\r
+int cat66121_sys_unplug(struct hdmi *hdmi);\r
+int cat66121_sys_detect_hpd(struct hdmi *hdmi, int *hpdstatus);\r
+int cat66121_sys_detect_sink(struct hdmi *hdmi, int *sink_status);\r
+int cat66121_sys_read_edid(struct hdmi *hdmi, int block, unsigned char *buff);\r
+int cat66121_sys_config_video(struct hdmi *hdmi, int vic, int input_color, int output_color);\r
+int cat66121_sys_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio);\r
+int cat66121_sys_config_hdcp(struct hdmi *hdmi, int enable);\r
+int cat66121_sys_enalbe_output(struct hdmi *hdmi, int enable);\r
+int cat66121_sys_check_status(struct hdmi *hdmi);\r
+#endif // _cat66121_SYS_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <config.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#ifndef _CONFIG_H_\r
+#define _CONFIG_H_\r
+#pragma message("config.h")\r
+\r
+#ifdef EXTERN_HDCPROM\r
+#pragma message("Defined EXTERN_HDCPROM")\r
+#endif // EXTERN_HDCPROM\r
+\r
+#define SUPPORT_EDID\r
+#define SUPPORT_HDCP\r
+//#define SUPPORT_SHA\r
+//#define SUPPORT_AUDIO_MONITOR\r
+#define AudioOutDelayCnt 250\r
+\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+// Video Configuration\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+// 2010/01/26 added a option to disable HDCP.\r
+#define SUPPORT_OUTPUTYUV\r
+#define SUPPORT_OUTPUTRGB\r
+// #define DISABLE_HDMITX_CSC\r
+\r
+#define SUPPORT_INPUTRGB\r
+#define SUPPORT_INPUTYUV444\r
+#define SUPPORT_INPUTYUV422\r
+// #define SUPPORT_SYNCEMBEDDED\r
+// #define SUPPORT_DEGEN\r
+#define NON_SEQUENTIAL_YCBCR422\r
+\r
+\r
+\r
+#define INPUT_COLOR_MODE F_MODE_RGB444\r
+//#define INPUT_COLOR_MODE F_MODE_YUV422\r
+//#define INPUT_COLOR_MODE F_MODE_YUV444\r
+\r
+#define INPUT_COLOR_DEPTH 24\r
+// #define INPUT_COLOR_DEPTH 30\r
+// #define INPUT_COLOR_DEPTH 36\r
+\r
+//#define OUTPUT_COLOR_MODE F_MODE_YUV422\r
+//#define OUTPUT_COLOR_MODE F_MODE_YUV444\r
+#define OUTPUT_COLOR_MODE F_MODE_RGB444\r
+\r
+//#define OUTPUT_3D_MODE Frame_Pcaking\r
+//#define OUTPUT_3D_MODE Top_and_Botton\r
+//#define OUTPUT_3D_MODE Side_by_Side\r
+\r
+// #define INV_INPUT_ACLK\r
+#define INV_INPUT_PCLK\r
+\r
+#ifdef SUPPORT_SYNCEMBEDDED\r
+ // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB) // 16 bit sync embedded\r
+ // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded\r
+ #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR|T_MODE_PCLKDIV2) // 16 bit sync embedded DDR\r
+ // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR) // 8 bit sync embedded DDR\r
+\r
+ #define SUPPORT_INPUTYUV422\r
+ #ifdef INPUT_COLOR_MODE\r
+ #undef INPUT_COLOR_MODE\r
+ #endif // INPUT_COLOR_MODE\r
+ #define INPUT_COLOR_MODE F_MODE_YUV422\r
+#else\r
+ #pragma message ("Defined seperated sync.")\r
+ #define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate\r
+ //#define INPUT_SIGNAL_TYPE ( T_MODE_DEGEN )\r
+ //#define INPUT_SIGNAL_TYPE ( T_MODE_INDDR)\r
+ //#define INPUT_SIGNAL_TYPE ( T_MODE_SYNCEMB)\r
+ //#define INPUT_SIGNAL_TYPE ( T_MODE_CCIR656 | T_MODE_SYNCEMB )\r
+#endif\r
+\r
+\r
+#if defined(SUPPORT_INPUTYUV444) || defined(SUPPORT_INPUTYUV422)\r
+#define SUPPORT_INPUTYUV\r
+#endif\r
+\r
+#ifdef SUPPORT_SYNCEMBEDDED\r
+#pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.")\r
+#endif\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+// Audio Configuration\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+\r
+// #define SUPPORT_HBR_AUDIO\r
+#define USE_SPDIF_CHSTAT\r
+#ifndef SUPPORT_HBR_AUDIO\r
+ #define INPUT_SAMPLE_FREQ AUDFS_48KHz\r
+ #define INPUT_SAMPLE_FREQ_HZ 48000L\r
+ #define OUTPUT_CHANNEL 2 // 3 // 4 // 5//6 //7 //8\r
+\r
+ #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM\r
+ // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM\r
+ #define CONFIG_INPUT_AUDIO_SPDIF FALSE // I2S\r
+ // #define CONFIG_INPUT_AUDIO_SPDIF TRUE // SPDIF\r
+\r
+ // #define I2S_FORMAT 0x00 // 24bit I2S audio\r
+ #define I2S_FORMAT 0x01 // 32bit I2S audio\r
+ // #define I2S_FORMAT 0x02 // 24bit I2S audio, right justify\r
+ // #define I2S_FORMAT 0x03 // 32bit I2S audio, right justify\r
+\r
+#else // SUPPORT_HBR_AUDIO\r
+\r
+ #define INPUT_SAMPLE_FREQ AUDFS_768KHz\r
+ #define INPUT_SAMPLE_FREQ_HZ 768000L\r
+ #define OUTPUT_CHANNEL 8\r
+ #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR\r
+ #define CONFIG_INPUT_AUDIO_SPDIF FALSE // I2S\r
+ // #define CONFIG_INPUT_AUDIO_SPDIF TRUE // SPDIF\r
+ #define I2S_FORMAT 0x47 // 32bit audio\r
+#endif\r
+\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+// Audio Monitor Configuration\r
+//////////////////////////////////////////////////////////////////////////////////////////\r
+// #define HDMITX_AUTO_MONITOR_INPUT\r
+// #define HDMITX_INPUT_INFO\r
+\r
+#ifdef HDMITX_AUTO_MONITOR_INPUT\r
+#define HDMITX_INPUT_INFO\r
+#endif\r
+\r
+\r
+#endif\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <csc.c>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/01/06\r
+// @fileversion: COMMON_2.00\r
+//******************************************/\r
+\r
+#include "config.h"\r
+#include "typedef.h"\r
+\r
+#if (defined (SUPPORT_OUTPUTYUV)) && (defined (SUPPORT_INPUTRGB))\r
+\r
+ BYTE _CODE bCSCMtx_RGB2YUV_ITU601_16_235[] =\r
+ {\r
+ 0x00,0x80,0x00,\r
+ 0xB2,0x04,0x65,0x02,0xE9,0x00,\r
+ 0x93,0x3C,0x18,0x04,0x55,0x3F,\r
+ 0x49,0x3D,0x9F,0x3E,0x18,0x04\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_RGB2YUV_ITU601_0_255[] =\r
+ {\r
+ 0x10,0x80,0x10,\r
+ 0x09,0x04,0x0E,0x02,0xC9,0x00,\r
+ 0x0F,0x3D,0x84,0x03,0x6D,0x3F,\r
+ 0xAB,0x3D,0xD1,0x3E,0x84,0x03\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_RGB2YUV_ITU709_16_235[] =\r
+ {\r
+ 0x00,0x80,0x00,\r
+ 0xB8,0x05,0xB4,0x01,0x94,0x00,\r
+ 0x4a,0x3C,0x17,0x04,0x9F,0x3F,\r
+ 0xD9,0x3C,0x10,0x3F,0x17,0x04\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_RGB2YUV_ITU709_0_255[] =\r
+ {\r
+ 0x10,0x80,0x10,\r
+ 0xEa,0x04,0x77,0x01,0x7F,0x00,\r
+ 0xD0,0x3C,0x83,0x03,0xAD,0x3F,\r
+ 0x4B,0x3D,0x32,0x3F,0x83,0x03\r
+ } ;\r
+#endif\r
+\r
+#if (defined (SUPPORT_OUTPUTRGB)) && (defined (SUPPORT_INPUTYUV))\r
+\r
+ BYTE _CODE bCSCMtx_YUV2RGB_ITU601_16_235[] =\r
+ {\r
+ 0x00,0x00,0x00,\r
+ 0x00,0x08,0x6B,0x3A,0x50,0x3D,\r
+ 0x00,0x08,0xF5,0x0A,0x02,0x00,\r
+ 0x00,0x08,0xFD,0x3F,0xDA,0x0D\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_YUV2RGB_ITU601_0_255[] =\r
+ {\r
+ 0x04,0x00,0xA7,\r
+ 0x4F,0x09,0x81,0x39,0xDD,0x3C,\r
+ 0x4F,0x09,0xC4,0x0C,0x01,0x00,\r
+ 0x4F,0x09,0xFD,0x3F,0x1F,0x10\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_YUV2RGB_ITU709_16_235[] =\r
+ {\r
+ 0x00,0x00,0x00,\r
+ 0x00,0x08,0x55,0x3C,0x88,0x3E,\r
+ 0x00,0x08,0x51,0x0C,0x00,0x00,\r
+ 0x00,0x08,0x00,0x00,0x84,0x0E\r
+ } ;\r
+\r
+ BYTE _CODE bCSCMtx_YUV2RGB_ITU709_0_255[] =\r
+ {\r
+ 0x04,0x00,0xA7,\r
+ 0x4F,0x09,0xBA,0x3B,0x4B,0x3E,\r
+ 0x4F,0x09,0x57,0x0E,0x02,0x00,\r
+ 0x4F,0x09,0xFE,0x3F,0xE8,0x10\r
+ } ;\r
+#endif\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <debug.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#ifndef _DEBUG_H_\r
+#define _DEBUG_H_\r
+#define Debug_message 1\r
+\r
+#pragma message("debug.h")\r
+\r
+#ifndef Debug_message\r
+#define Debug_message 1\r
+#endif\r
+\r
+#if Debug_message\r
+\r
+ #define HDMITX_DEBUG_PRINTF(x) printk x\r
+ #define HDCP_DEBUG_PRINTF(x) printk x\r
+ #define EDID_DEBUG_PRINTF(x) printk x\r
+ #define HDMITX_DEBUG_INFO(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF(x)\r
+ #define HDCP_DEBUG_PRINTF(x)\r
+ #define EDID_DEBUG_PRINTF(x)\r
+ #define HDMITX_DEBUG_INFO(x)\r
+#endif\r
+\r
+\r
+#if( Debug_message & (1<<1))\r
+ #define HDMITX_DEBUG_PRINTF1(x) printk x\r
+ #define HDCP_DEBUG_PRINTF1(x) printk x\r
+ #define EDID_DEBUG_PRINTF1(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF1(x)\r
+ #define HDCP_DEBUG_PRINTF1(x)\r
+ #define EDID_DEBUG_PRINTF1(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<2))\r
+ #define HDMITX_DEBUG_PRINTF2(x) printk x\r
+ #define HDCP_DEBUG_PRINTF2(x) printk x\r
+ #define EDID_DEBUG_PRINTF2(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF2(x)\r
+ #define HDCP_DEBUG_PRINTF2(x)\r
+ #define EDID_DEBUG_PRINTF2(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<3))\r
+ #define HDMITX_DEBUG_PRINTF3(x) printk x\r
+ #define HDCP_DEBUG_PRINTF3(x) printk x\r
+ #define EDID_DEBUG_PRINTF3(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF3(x)\r
+ #define HDCP_DEBUG_PRINTF3(x)\r
+ #define EDID_DEBUG_PRINTF3(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<4))\r
+ #define HDMITX_DEBUG_PRINTF4(x) printk x\r
+ #define HDCP_DEBUG_PRINTF4(x) printk x\r
+ #define EDID_DEBUG_PRINTF4(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF4(x)\r
+ #define HDCP_DEBUG_PRINTF4(x)\r
+ #define EDID_DEBUG_PRINTF4(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<5))\r
+ #define HDMITX_DEBUG_PRINTF5(x) printk x\r
+ #define HDCP_DEBUG_PRINTF5(x) printk x\r
+ #define EDID_DEBUG_PRINTF5(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF5(x)\r
+ #define HDCP_DEBUG_PRINTF5(x)\r
+ #define EDID_DEBUG_PRINTF5(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<6))\r
+ #define HDMITX_DEBUG_PRINTF6(x) printk x\r
+ #define HDCP_DEBUG_PRINTF6(x) printk x\r
+ #define EDID_DEBUG_PRINTF6(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF6(x)\r
+ #define HDCP_DEBUG_PRINTF6(x)\r
+ #define EDID_DEBUG_PRINTF6(x)\r
+#endif\r
+\r
+#if( Debug_message & (1<<7))\r
+ #define HDMITX_DEBUG_PRINTF7(x) printk x\r
+ #define HDCP_DEBUG_PRINTF7(x) printk x\r
+ #define EDID_DEBUG_PRINTF7(x) printk x\r
+#else\r
+ #define HDMITX_DEBUG_PRINTF7(x)\r
+ #define HDCP_DEBUG_PRINTF7(x)\r
+ #define EDID_DEBUG_PRINTF7(x)\r
+#endif\r
+\r
+\r
+#endif// _DEBUG_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+#ifndef _HDMITX_H_\r
+#define _HDMITX_H_\r
+#include <linux/kernel.h>\r
+#include <linux/delay.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/i2c.h>\r
+\r
+#include "debug.h"\r
+#include "config.h"\r
+#include "typedef.h"\r
+#include "hdmitx_drv.h"\r
+\r
+#define HDMITX_MAX_DEV_COUNT 1\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////\r
+// Output Mode Type\r
+///////////////////////////////////////////////////////////////////////\r
+\r
+#define RES_ASPEC_4x3 0\r
+#define RES_ASPEC_16x9 1\r
+#define F_MODE_REPT_NO 0\r
+#define F_MODE_REPT_TWICE 1\r
+#define F_MODE_REPT_QUATRO 3\r
+#define F_MODE_CSC_ITU601 0\r
+#define F_MODE_CSC_ITU709 1\r
+\r
+\r
+#define TIMER_LOOP_LEN 10\r
+#define MS(x) (((x)+(TIMER_LOOP_LEN-1))/TIMER_LOOP_LEN); // for timer loop\r
+\r
+// #define SUPPORT_AUDI_AudSWL 16 // Jeilin case.\r
+#define SUPPORT_AUDI_AudSWL 24 // Jeilin case.\r
+\r
+#if(SUPPORT_AUDI_AudSWL==16)\r
+ #define CHTSTS_SWCODE 0x02\r
+#elif(SUPPORT_AUDI_AudSWL==18)\r
+ #define CHTSTS_SWCODE 0x04\r
+#elif(SUPPORT_AUDI_AudSWL==20)\r
+ #define CHTSTS_SWCODE 0x03\r
+#else\r
+ #define CHTSTS_SWCODE 0x0B\r
+#endif\r
+\r
+#endif // _HDMITX_H_\r
+\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_drv.c>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+/////////////////////////////////////////////////////////////////////\r
+// HDMITX.C\r
+// Driver code for platform independent\r
+/////////////////////////////////////////////////////////////////////\r
+#include "hdmitx.h"\r
+#include "hdmitx_drv.h"\r
+#define FALLING_EDGE_TRIGGER\r
+\r
+#define MSCOUNT 1000\r
+#define LOADING_UPDATE_TIMEOUT (3000/32) // 3sec\r
+// USHORT u8msTimer = 0 ;\r
+// USHORT TimerServF = TRUE ;\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Authentication status\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+// #define TIMEOUT_WAIT_AUTH MS(2000)\r
+\r
+HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT] ;\r
+\r
+#ifndef INV_INPUT_PCLK\r
+#define PCLKINV 0\r
+#else\r
+#define PCLKINV B_TX_VDO_LATCH_EDGE\r
+#endif\r
+\r
+#ifndef INV_INPUT_ACLK\r
+ #define InvAudCLK 0\r
+#else\r
+ #define InvAudCLK B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS\r
+#endif\r
+\r
+#define INIT_CLK_HIGH\r
+// #define INIT_CLK_LOW\r
+\r
+_CODE RegSetEntry HDMITX_Init_Table[] = {\r
+\r
+ {0x0F, 0x40, 0x00},\r
+\r
+ {0x62, 0x08, 0x00},\r
+ {0x64, 0x04, 0x00},\r
+ {0x01,0x00,0x00},//idle(100);\r
+\r
+ {0x04, 0x20, 0x20},\r
+ {0x04, 0x1D, 0x1D},\r
+ {0x01,0x00,0x00},//idle(100);\r
+ {0x0F, 0x01, 0x00}, // bank 0 ;\r
+ #ifdef INIT_CLK_LOW\r
+ {0x62, 0x90, 0x10},\r
+ {0x64, 0x89, 0x09},\r
+ {0x68, 0x10, 0x10},\r
+ #endif\r
+\r
+ {0xD1, 0x0E, 0x0C},\r
+ {0x65, 0x03, 0x00},\r
+ #ifdef NON_SEQUENTIAL_YCBCR422 // for ITE HDMIRX\r
+ {0x71, 0xFC, 0x1C},\r
+ #else\r
+ {0x71, 0xFC, 0x18},\r
+ #endif\r
+\r
+ {0x8D, 0xFF, CEC_I2C_SLAVE_ADDR},\r
+ {0x0F, 0x08, 0x08},\r
+\r
+ {0xF8,0xFF,0xC3},\r
+ {0xF8,0xFF,0xA5},\r
+ {0x20, 0x80, 0x80},\r
+ {0x37, 0x01, 0x00},\r
+ {0x20, 0x80, 0x00},\r
+ {0xF8,0xFF,0xFF},\r
+\r
+ {0x59, 0xD8, 0x40|PCLKINV},\r
+ {0xE1, 0x20, InvAudCLK},\r
+ {0x05, 0xC0, 0x40},\r
+ {REG_TX_INT_MASK1, 0xFF, ~(B_TX_RXSEN_MASK|B_TX_HPD_MASK)},\r
+ {REG_TX_INT_MASK2, 0xFF, ~(B_TX_KSVLISTCHK_MASK|B_TX_AUTH_DONE_MASK|B_TX_AUTH_FAIL_MASK)},\r
+ {REG_TX_INT_MASK3, 0xFF, ~(B_TX_VIDSTABLE_MASK)},\r
+ {0x0C, 0xFF, 0xFF},\r
+ {0x0D, 0xFF, 0xFF},\r
+ {0x0E, 0x03, 0x03},\r
+\r
+ {0x0C, 0xFF, 0x00},\r
+ {0x0D, 0xFF, 0x00},\r
+ {0x0E, 0x02, 0x00},\r
+ {0x09, 0x03, 0x00}, // Enable HPD and RxSen Interrupt\r
+ {0,0,0}\r
+};\r
+\r
+_CODE RegSetEntry HDMITX_DefaultVideo_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default output format.\r
+ ////////////////////////////////////////////////////\r
+ {0x72, 0xff, 0x00},\r
+ {0x70, 0xff, 0x00},\r
+#ifndef DEFAULT_INPUT_YCBCR\r
+// GenCSC\RGB2YUV_ITU709_16_235.c\r
+ {0x72, 0xFF, 0x02},\r
+ {0x73, 0xFF, 0x00},\r
+ {0x74, 0xFF, 0x80},\r
+ {0x75, 0xFF, 0x00},\r
+ {0x76, 0xFF, 0xB8},\r
+ {0x77, 0xFF, 0x05},\r
+ {0x78, 0xFF, 0xB4},\r
+ {0x79, 0xFF, 0x01},\r
+ {0x7A, 0xFF, 0x93},\r
+ {0x7B, 0xFF, 0x00},\r
+ {0x7C, 0xFF, 0x49},\r
+ {0x7D, 0xFF, 0x3C},\r
+ {0x7E, 0xFF, 0x18},\r
+ {0x7F, 0xFF, 0x04},\r
+ {0x80, 0xFF, 0x9F},\r
+ {0x81, 0xFF, 0x3F},\r
+ {0x82, 0xFF, 0xD9},\r
+ {0x83, 0xFF, 0x3C},\r
+ {0x84, 0xFF, 0x10},\r
+ {0x85, 0xFF, 0x3F},\r
+ {0x86, 0xFF, 0x18},\r
+ {0x87, 0xFF, 0x04},\r
+#else\r
+// GenCSC\YUV2RGB_ITU709_16_235.c\r
+ {0x0F, 0x01, 0x00},\r
+ {0x72, 0xFF, 0x03},\r
+ {0x73, 0xFF, 0x00},\r
+ {0x74, 0xFF, 0x80},\r
+ {0x75, 0xFF, 0x00},\r
+ {0x76, 0xFF, 0x00},\r
+ {0x77, 0xFF, 0x08},\r
+ {0x78, 0xFF, 0x53},\r
+ {0x79, 0xFF, 0x3C},\r
+ {0x7A, 0xFF, 0x89},\r
+ {0x7B, 0xFF, 0x3E},\r
+ {0x7C, 0xFF, 0x00},\r
+ {0x7D, 0xFF, 0x08},\r
+ {0x7E, 0xFF, 0x51},\r
+ {0x7F, 0xFF, 0x0C},\r
+ {0x80, 0xFF, 0x00},\r
+ {0x81, 0xFF, 0x00},\r
+ {0x82, 0xFF, 0x00},\r
+ {0x83, 0xFF, 0x08},\r
+ {0x84, 0xFF, 0x00},\r
+ {0x85, 0xFF, 0x00},\r
+ {0x86, 0xFF, 0x87},\r
+ {0x87, 0xFF, 0x0E},\r
+#endif\r
+ // 2012/12/20 added by Keming's suggestion test\r
+ {0x88, 0xF0, 0x00},\r
+ //~jauchih.tseng@ite.com.tw\r
+ {0x04, 0x08, 0x00},\r
+ {0,0,0}\r
+};\r
+_CODE RegSetEntry HDMITX_SetHDMI_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default HDMI Mode\r
+ ////////////////////////////////////////////////////\r
+ {0xC0, 0x01, 0x01},\r
+ {0xC1, 0x03, 0x03},\r
+ {0xC6, 0x03, 0x03},\r
+ {0,0,0}\r
+};\r
+\r
+_CODE RegSetEntry HDMITX_SetDVI_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default HDMI Mode\r
+ ////////////////////////////////////////////////////\r
+ {0x0F, 0x01, 0x01},\r
+ {0x58, 0xFF, 0x00},\r
+ {0x0F, 0x01, 0x00},\r
+ {0xC0, 0x01, 0x00},\r
+ {0xC1, 0x03, 0x02},\r
+ {0xC6, 0x03, 0x00},\r
+ {0,0,0}\r
+};\r
+\r
+_CODE RegSetEntry HDMITX_DefaultAVIInfo_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default avi infoframe\r
+ ////////////////////////////////////////////////////\r
+ {0x0F, 0x01, 0x01},\r
+ {0x58, 0xFF, 0x10},\r
+ {0x59, 0xFF, 0x08},\r
+ {0x5A, 0xFF, 0x00},\r
+ {0x5B, 0xFF, 0x00},\r
+ {0x5C, 0xFF, 0x00},\r
+ {0x5D, 0xFF, 0x57},\r
+ {0x5E, 0xFF, 0x00},\r
+ {0x5F, 0xFF, 0x00},\r
+ {0x60, 0xFF, 0x00},\r
+ {0x61, 0xFF, 0x00},\r
+ {0x62, 0xFF, 0x00},\r
+ {0x63, 0xFF, 0x00},\r
+ {0x64, 0xFF, 0x00},\r
+ {0x65, 0xFF, 0x00},\r
+ {0x0F, 0x01, 0x00},\r
+ {0xCD, 0x03, 0x03},\r
+ {0,0,0}\r
+};\r
+_CODE RegSetEntry HDMITX_DeaultAudioInfo_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default audio infoframe\r
+ ////////////////////////////////////////////////////\r
+ {0x0F, 0x01, 0x01},\r
+ {0x68, 0xFF, 0x00},\r
+ {0x69, 0xFF, 0x00},\r
+ {0x6A, 0xFF, 0x00},\r
+ {0x6B, 0xFF, 0x00},\r
+ {0x6C, 0xFF, 0x00},\r
+ {0x6D, 0xFF, 0x71},\r
+ {0x0F, 0x01, 0x00},\r
+ {0xCE, 0x03, 0x03},\r
+\r
+ {0,0,0}\r
+};\r
+\r
+_CODE RegSetEntry HDMITX_Aud_CHStatus_LPCM_20bit_48Khz[] =\r
+{\r
+ {0x0F, 0x01, 0x01},\r
+ {0x33, 0xFF, 0x00},\r
+ {0x34, 0xFF, 0x18},\r
+ {0x35, 0xFF, 0x00},\r
+ {0x91, 0xFF, 0x00},\r
+ {0x92, 0xFF, 0x00},\r
+ {0x93, 0xFF, 0x01},\r
+ {0x94, 0xFF, 0x00},\r
+ {0x98, 0xFF, 0x02},\r
+ {0x99, 0xFF, 0xDA},\r
+ {0x0F, 0x01, 0x00},\r
+ {0,0,0}//end of table\r
+} ;\r
+\r
+_CODE RegSetEntry HDMITX_AUD_SPDIF_2ch_24bit[] =\r
+{\r
+ {0x0F, 0x11, 0x00},\r
+ {0x04, 0x14, 0x04},\r
+ {0xE0, 0xFF, 0xD1},\r
+ {0xE1, 0xFF, 0x01},\r
+ {0xE2, 0xFF, 0xE4},\r
+ {0xE3, 0xFF, 0x10},\r
+ {0xE4, 0xFF, 0x00},\r
+ {0xE5, 0xFF, 0x00},\r
+ {0x04, 0x14, 0x00},\r
+ {0,0,0}//end of table\r
+} ;\r
+\r
+_CODE RegSetEntry HDMITX_AUD_I2S_2ch_24bit[] =\r
+{\r
+ {0x0F, 0x11, 0x00},\r
+ {0x04, 0x14, 0x04},\r
+ {0xE0, 0xFF, 0xC1},\r
+ {0xE1, 0xFF, 0x01},\r
+ {0xE2, 0xFF, 0xE4},\r
+ {0xE3, 0xFF, 0x00},\r
+ {0xE4, 0xFF, 0x00},\r
+ {0xE5, 0xFF, 0x00},\r
+ {0x04, 0x14, 0x00},\r
+ {0,0,0}//end of table\r
+} ;\r
+\r
+_CODE RegSetEntry HDMITX_DefaultAudio_Table[] = {\r
+\r
+ ////////////////////////////////////////////////////\r
+ // Config default audio output format.\r
+ ////////////////////////////////////////////////////\r
+ {0x0F, 0x21, 0x00},\r
+ {0x04, 0x14, 0x04},\r
+ {0xE0, 0xFF, 0xC1},\r
+ {0xE1, 0xFF, 0x01},\r
+ {0xE2, 0xFF, 0xE4},\r
+ {0xE3, 0xFF, 0x00},\r
+ {0xE4, 0xFF, 0x00},\r
+ {0xE5, 0xFF, 0x00},\r
+ {0x0F, 0x01, 0x01},\r
+ {0x33, 0xFF, 0x00},\r
+ {0x34, 0xFF, 0x18},\r
+ {0x35, 0xFF, 0x00},\r
+ {0x91, 0xFF, 0x00},\r
+ {0x92, 0xFF, 0x00},\r
+ {0x93, 0xFF, 0x01},\r
+ {0x94, 0xFF, 0x00},\r
+ {0x98, 0xFF, 0x02},\r
+ {0x99, 0xFF, 0xDB},\r
+ {0x0F, 0x01, 0x00},\r
+ {0x04, 0x14, 0x00},\r
+\r
+ {0x00, 0x00, 0x00} // End of Table.\r
+} ;\r
+\r
+_CODE RegSetEntry HDMITX_PwrDown_Table[] = {\r
+ // Enable GRCLK\r
+ {0x0F, 0x40, 0x00},\r
+ // PLL Reset\r
+ {0x61, 0x10, 0x10}, // DRV_RST\r
+ {0x62, 0x08, 0x00}, // XP_RESETB\r
+ {0x64, 0x04, 0x00}, // IP_RESETB\r
+ {0x01, 0x00, 0x00}, // idle(100);\r
+\r
+ // PLL PwrDn\r
+ {0x61, 0x20, 0x20}, // PwrDn DRV\r
+ {0x62, 0x44, 0x44}, // PwrDn XPLL\r
+ {0x64, 0x40, 0x40}, // PwrDn IPLL\r
+\r
+ // HDMITX PwrDn\r
+ {0x05, 0x01, 0x01}, // PwrDn PCLK\r
+ {0x0F, 0x78, 0x78}, // PwrDn GRCLK\r
+ {0x00, 0x00, 0x00} // End of Table.\r
+};\r
+\r
+_CODE RegSetEntry HDMITX_PwrOn_Table[] = {\r
+ {0x0F, 0x78, 0x38}, // PwrOn GRCLK\r
+ {0x05, 0x01, 0x00}, // PwrOn PCLK\r
+\r
+ // PLL PwrOn\r
+ {0x61, 0x20, 0x00}, // PwrOn DRV\r
+ {0x62, 0x44, 0x00}, // PwrOn XPLL\r
+ {0x64, 0x40, 0x00}, // PwrOn IPLL\r
+\r
+ // PLL Reset OFF\r
+ {0x61, 0x10, 0x00}, // DRV_RST\r
+ {0x62, 0x08, 0x08}, // XP_RESETB\r
+ {0x64, 0x04, 0x04}, // IP_RESETB\r
+ {0x0F, 0x78, 0x08}, // PwrOn IACLK\r
+ {0x00, 0x00, 0x00} // End of Table.\r
+};\r
+\r
+#ifdef DETECT_VSYNC_CHG_IN_SAV\r
+BOOL EnSavVSync = FALSE ;\r
+#endif\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function Prototype\r
+//////////////////////////////////////////////////////////////////////\r
+void hdmitx_LoadRegSetting(RegSetEntry table[]);\r
+\r
+void HDMITX_InitTxDev(HDMITXDEV *pInstance)\r
+{\r
+ if(pInstance && 0 < HDMITX_MAX_DEV_COUNT)\r
+ {\r
+ hdmiTxDev[0] = *pInstance ;\r
+ }\r
+}\r
+\r
+void InitHDMITX()\r
+{\r
+ hdmitx_LoadRegSetting(HDMITX_Init_Table);\r
+ HDMITX_WriteI2C_Byte(REG_TX_PLL_CTRL,0xff);\r
+ hdmiTxDev[0].bIntPOL = (hdmiTxDev[0].bIntType&B_TX_INTPOL_ACTH)?TRUE:FALSE ;\r
+\r
+ // Avoid power loading in un play status.\r
+ //////////////////////////////////////////////////////////////////\r
+ // Setup HDCP ROM\r
+ //////////////////////////////////////////////////////////////////\r
+#ifdef HDMITX_INPUT_INFO\r
+ hdmiTxDev[0].RCLK = CalcRCLK();\r
+#endif\r
+ hdmitx_LoadRegSetting(HDMITX_DefaultVideo_Table);\r
+ hdmitx_LoadRegSetting(HDMITX_SetHDMI_Table);\r
+ hdmitx_LoadRegSetting(HDMITX_DefaultAVIInfo_Table);\r
+ hdmitx_LoadRegSetting(HDMITX_DeaultAudioInfo_Table);\r
+ hdmitx_LoadRegSetting(HDMITX_Aud_CHStatus_LPCM_20bit_48Khz);\r
+ hdmitx_LoadRegSetting(HDMITX_AUD_SPDIF_2ch_24bit);\r
+\r
+ HDMITX_DEBUG_PRINTF((\r
+ "-----------------------------------------------------\n"\r
+ "Init HDMITX\n"\r
+ "-----------------------------------------------------\n"));\r
+\r
+ DumpHDMITXReg();\r
+}\r
+\r
+BOOL getHDMITX_LinkStatus()\r
+{\r
+ if(B_TX_RXSENDETECT & HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS))\r
+ {\r
+ if(0==HDMITX_ReadI2C_Byte(REG_TX_AFE_DRV_CTRL))\r
+ {\r
+ //HDMITX_DEBUG_PRINTF(("getHDMITX_LinkStatus()!!\n") );\r
+ return TRUE;\r
+ }\r
+ }\r
+ //HDMITX_DEBUG_PRINTF(("GetTMDS not Ready()!!\n") );\r
+\r
+ return FALSE;\r
+}\r
+\r
+BYTE CheckHDMITX(BYTE *pHPD,BYTE *pHPDChange)\r
+{\r
+ BYTE intdata1,intdata2,intdata3,sysstat;\r
+ BYTE intclr3 = 0 ;\r
+ BYTE PrevHPD = hdmiTxDev[0].bHPD ;\r
+ BYTE HPD ;\r
+ sysstat = HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS);\r
+ // HDMITX_DEBUG_PRINTF(("REG_TX_SYS_STATUS = %X \n",sysstat));\r
+\r
+ if((sysstat & (B_TX_HPDETECT/*|B_TX_RXSENDETECT*/)) == (B_TX_HPDETECT/*|B_TX_RXSENDETECT*/))\r
+ {\r
+ HPD = TRUE;\r
+ }\r
+ else\r
+ {\r
+ HPD = FALSE;\r
+ }\r
+ // CheckClockStable(sysstat);\r
+ // 2007/06/20 added by jj_tseng@chipadvanced.com\r
+\r
+ if(pHPDChange)\r
+ {\r
+ *pHPDChange = (HPD!=PrevHPD)?TRUE:FALSE ; // default give pHPDChange value compared to previous HPD value.\r
+\r
+ }\r
+ //~jj_tseng@chipadvanced.com 2007/06/20\r
+\r
+ if(HPD==FALSE)\r
+ {\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+ }\r
+ if(sysstat & B_TX_INT_ACTIVE)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("REG_TX_SYS_STATUS = 0x%02X \n",(int)sysstat));\r
+\r
+ intdata1 = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1);\r
+ HDMITX_DEBUG_PRINTF(("INT_Handler: reg%X = %X\n",(int)REG_TX_INT_STAT1,(int)intdata1));\r
+ if(intdata1 & B_TX_INT_AUD_OVERFLOW)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("B_TX_INT_AUD_OVERFLOW.\n"));\r
+ HDMITX_OrReg_Byte(REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST));\r
+ HDMITX_AndReg_Byte(REG_TX_SW_RST,~(B_HDMITX_AUD_RST|B_TX_AREF_RST));\r
+ //AudioDelayCnt=AudioOutDelayCnt;\r
+ //LastRefaudfreqnum=0;\r
+ }\r
+ if(intdata1 & B_TX_INT_DDCFIFO_ERR)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("DDC FIFO Error.\n"));\r
+ hdmitx_ClearDDCFIFO();\r
+ hdmiTxDev[0].bAuthenticated= FALSE ;\r
+ }\r
+ if(intdata1 & B_TX_INT_DDC_BUS_HANG)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("DDC BUS HANG.\n"));\r
+ hdmitx_AbortDDC();\r
+\r
+ if(hdmiTxDev[0].bAuthenticated)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("when DDC hang,and aborted DDC,the HDCP authentication need to restart.\n"));\r
+ #ifdef SUPPORT_HDCP\r
+ hdmitx_hdcp_ResumeAuthentication();\r
+ #endif\r
+ }\r
+ }\r
+ if(intdata1 & (B_TX_INT_HPD_PLUG/*|B_TX_INT_RX_SENSE*/))\r
+ {\r
+\r
+ if(pHPDChange)\r
+ {\r
+ *pHPDChange = TRUE ;\r
+ }\r
+ if(HPD == FALSE)\r
+ {\r
+ /*\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST,B_TX_AREF_RST|B_HDMITX_VID_RST|B_HDMITX_AUD_RST|B_TX_HDCP_RST_HDMITX);\r
+ delay1ms(1);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST|B_TX_AFE_DRV_PWD);\r
+ */\r
+ //HDMITX_DEBUG_PRINTF(("Unplug,%x %x\n",(int)HDMITX_ReadI2C_Byte(REG_TX_SW_RST),(int)HDMITX_ReadI2C_Byte(REG_TX_AFE_DRV_CTRL)));\r
+ }\r
+ }\r
+ if(intdata1 & (B_TX_INT_RX_SENSE))\r
+ {\r
+ hdmiTxDev[0].bAuthenticated = FALSE;\r
+ }\r
+ intdata2 = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT2);\r
+ HDMITX_DEBUG_PRINTF(("INT_Handler: reg%X = %X\n",(int)REG_TX_INT_STAT2,(int)intdata2));\r
+\r
+ #ifdef SUPPORT_HDCP\r
+ if(intdata2 & B_TX_INT_AUTH_DONE)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("interrupt Authenticate Done.\n"));\r
+ HDMITX_OrReg_Byte(REG_TX_INT_MASK2,(BYTE)B_TX_AUTH_DONE_MASK);\r
+ //hdmiTxDev[0].bAuthenticated = TRUE ;\r
+ //setHDMITX_AVMute(FALSE);\r
+ }\r
+ if(intdata2 & B_TX_INT_AUTH_FAIL)\r
+ {\r
+ hdmiTxDev[0].bAuthenticated = FALSE;\r
+ //HDMITX_DEBUG_PRINTF(("interrupt Authenticate Fail.\n"));\r
+ hdmitx_AbortDDC(); // @emily add\r
+ //hdmitx_hdcp_ResumeAuthentication();\r
+ }\r
+ #endif // SUPPORT_HDCP\r
+\r
+ /*\r
+ intdata3 = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT3);\r
+ if(intdata3 & B_TX_INT_VIDSTABLE)\r
+ {\r
+ sysstat = HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS);\r
+ if(sysstat & B_TXVIDSTABLE)\r
+ {\r
+ hdmitx_FireAFE();\r
+ }\r
+ }\r
+ */\r
+ intdata3= HDMITX_ReadI2C_Byte(0xEE);\r
+ if( intdata3 )\r
+ {\r
+ HDMITX_WriteI2C_Byte(0xEE,intdata3); // clear ext interrupt ;\r
+ HDMITX_DEBUG_PRINTF(("%s%s%s%s%s%s%s\n",\r
+ (intdata3&0x40)?"video parameter change ":"",\r
+ (intdata3&0x20)?"HDCP Pj check done ":"",\r
+ (intdata3&0x10)?"HDCP Ri check done ":"",\r
+ (intdata3&0x8)? "DDC bus hang ":"",\r
+ (intdata3&0x4)? "Video input FIFO auto reset ":"",\r
+ (intdata3&0x2)? "No audio input interrupt ":"",\r
+ (intdata3&0x1)? "Audio decode error interrupt ":""));\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR0,0xFF);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR1,0xFF);\r
+ intclr3 = (HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS))|B_TX_CLR_AUD_CTS | B_TX_INTACTDONE ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,intclr3); // clear interrupt.\r
+ intclr3 &= ~(B_TX_INTACTDONE);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,intclr3); // INTACTDONE reset to zero.\r
+ }\r
+ //\r
+ // else\r
+ // {\r
+ // if(pHPDChange)\r
+ // {\r
+ // if(HPD != PrevHPD)\r
+ // {\r
+ // *pHPDChange = TRUE;\r
+ // }\r
+ // else\r
+ // {\r
+ // *pHPDChange = FALSE;\r
+ // }\r
+ // }\r
+ // }\r
+ if(pHPDChange)\r
+ {\r
+ if((*pHPDChange==TRUE) &&(HPD==FALSE))\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST|B_TX_AFE_DRV_PWD);\r
+ }\r
+ }\r
+ if(pHPD)\r
+ {\r
+ *pHPD = HPD ;\r
+ }\r
+ hdmiTxDev[0].bHPD = HPD ;\r
+ return HPD ;\r
+}\r
+\r
+void HDMITX_PowerOn()\r
+{\r
+ hdmitx_LoadRegSetting(HDMITX_PwrOn_Table);\r
+}\r
+\r
+void HDMITX_PowerDown()\r
+{\r
+ hdmitx_LoadRegSetting(HDMITX_PwrDown_Table);\r
+}\r
+\r
+void setHDMITX_AVMute(BYTE bEnable)\r
+{\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_SetI2C_Byte(REG_TX_GCP,B_TX_SETAVMUTE, bEnable?B_TX_SETAVMUTE:0 );\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_GENERAL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_LoadRegSetting()\r
+// Input: RegSetEntry SettingTable[] ;\r
+// Return: N/A\r
+// Remark: if an entry {0, 0, 0} will be terminated.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_LoadRegSetting(RegSetEntry table[])\r
+{\r
+ int i ;\r
+\r
+ for( i = 0 ; ; i++ )\r
+ {\r
+ if( table[i].offset == 0 && table[i].invAndMask == 0 && table[i].OrMask == 0 )\r
+ {\r
+ return ;\r
+ }\r
+ else if( table[i].invAndMask == 0 && table[i].OrMask == 0 )\r
+ {\r
+ HDMITX_DEBUG_PRINTF2(("delay(%d)\n",(int)table[i].offset));\r
+ delay1ms(table[i].offset);\r
+ }\r
+ else if( table[i].invAndMask == 0xFF )\r
+ {\r
+ HDMITX_DEBUG_PRINTF2(("HDMITX_WriteI2C_Byte(%02x,%02x)\n",(int)table[i].offset,(int)table[i].OrMask));\r
+ HDMITX_WriteI2C_Byte(table[i].offset,table[i].OrMask);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_DEBUG_PRINTF2(("HDMITX_SetI2C_Byte(%02x,%02x,%02x)\n",(int)table[i].offset,(int)table[i].invAndMask,(int)table[i].OrMask));\r
+ HDMITX_SetI2C_Byte(table[i].offset,table[i].invAndMask,table[i].OrMask);\r
+ }\r
+ }\r
+}\r
+\r
+///*****************************************\r
+// @file <hdmitx_ddc.c>\r
+//******************************************/\r
+\r
+BOOL getHDMITX_EDIDBlock(int EDIDBlockID,BYTE *pEDIDData)\r
+{\r
+ if(!pEDIDData)\r
+ {\r
+ return FALSE ;\r
+ }\r
+ if(getHDMITX_EDIDBytes(pEDIDData,EDIDBlockID/2,(EDIDBlockID%2)*128,128) == ER_FAIL)\r
+ {\r
+ return FALSE ;\r
+ }\r
+ return TRUE ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: getHDMITX_EDIDBytes\r
+// Parameter: pData - the pointer of buffer to receive EDID ucdata.\r
+// bSegment - the segment of EDID readback.\r
+// offset - the offset of EDID ucdata in the segment. in byte.\r
+// count - the read back bytes count,cannot exceed 32\r
+// Return: ER_SUCCESS if successfully getting EDID. ER_FAIL otherwise.\r
+// Remark: function for read EDID ucdata from reciever.\r
+// Side-Effect: DDC master will set to be HOST. DDC FIFO will be used and dirty.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS getHDMITX_EDIDBytes(BYTE *pData,BYTE bSegment,BYTE offset,SHORT Count)\r
+{\r
+ SHORT RemainedCount,ReqCount ;\r
+ BYTE bCurrOffset ;\r
+ SHORT TimeOut ;\r
+ BYTE *pBuff = pData ;\r
+ BYTE ucdata ;\r
+\r
+ // HDMITX_DEBUG_PRINTF(("getHDMITX_EDIDBytes(%08lX,%d,%d,%d)\n",(ULONG)pData,(int)bSegment,(int)offset,(int)Count));\r
+ if(!pData)\r
+ {\r
+// HDMITX_DEBUG_PRINTF(("getHDMITX_EDIDBytes(): Invallid pData pointer %08lX\n",(ULONG)pData));\r
+ return ER_FAIL ;\r
+ }\r
+ if(HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1) & B_TX_INT_DDC_BUS_HANG)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("Called hdmitx_AboutDDC()\n"));\r
+ hdmitx_AbortDDC();\r
+\r
+ }\r
+ // HDMITX_OrReg_Byte(REG_TX_INT_CTRL,(1<<1));\r
+\r
+ hdmitx_ClearDDCFIFO();\r
+\r
+ RemainedCount = Count ;\r
+ bCurrOffset = offset ;\r
+\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ while(RemainedCount > 0)\r
+ {\r
+\r
+ ReqCount = (RemainedCount > DDC_FIFO_MAXREQ)?DDC_FIFO_MAXREQ:RemainedCount ;\r
+ HDMITX_DEBUG_PRINTF(("getHDMITX_EDIDBytes(): ReqCount = %d,bCurrOffset = %d\n",(int)ReqCount,(int)bCurrOffset));\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_FIFO_CLR);\r
+\r
+ for(TimeOut = 0 ; TimeOut < 200 ; TimeOut++)\r
+ {\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+\r
+ if(ucdata&B_TX_DDC_DONE)\r
+ {\r
+ break ;\r
+ }\r
+ if((ucdata & B_TX_DDC_ERROR)||(HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1) & B_TX_INT_DDC_BUS_HANG))\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("Called hdmitx_AboutDDC()\n"));\r
+ hdmitx_AbortDDC();\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_HEADER,DDC_EDID_ADDRESS); // for EDID ucdata get\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQOFF,bCurrOffset);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQCOUNT,(BYTE)ReqCount);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_EDIDSEG,bSegment);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_EDID_READ);\r
+\r
+ bCurrOffset += ReqCount ;\r
+ RemainedCount -= ReqCount ;\r
+\r
+ for(TimeOut = 250 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ delay1ms(1);\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+ if(ucdata & B_TX_DDC_DONE)\r
+ {\r
+ break ;\r
+ }\r
+ if(ucdata & B_TX_DDC_ERROR)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("getHDMITX_EDIDBytes(): DDC_STATUS = %02X,fail.\n",(int)ucdata));\r
+ // HDMITX_AndReg_Byte(REG_TX_INT_CTRL,~(1<<1));\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("getHDMITX_EDIDBytes(): DDC TimeOut. \n",(int)ucdata));\r
+ // HDMITX_AndReg_Byte(REG_TX_INT_CTRL,~(1<<1));\r
+ return ER_FAIL ;\r
+ }\r
+ do\r
+ {\r
+ *(pBuff++) = HDMITX_ReadI2C_Byte(REG_TX_DDC_READFIFO);\r
+ ReqCount -- ;\r
+ }while(ReqCount > 0);\r
+\r
+ }\r
+ // HDMITX_AndReg_Byte(REG_TX_INT_CTRL,~(1<<1));\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+/////////////////////////////\r
+// DDC Function.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_ClearDDCFIFO\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: clear the DDC FIFO.\r
+// Side-Effect: DDC master will set to be HOST.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_ClearDDCFIFO()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_FIFO_CLR);\r
+}\r
+\r
+void hdmitx_GenerateDDCSCLK()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_GEN_SCLCLK);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_AbortDDC\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: Force abort DDC and reset DDC bus.\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_AbortDDC()\r
+{\r
+ BYTE CPDesire,SWReset,DDCMaster ;\r
+ BYTE uc, timeout, i ;\r
+ // save the SW reset,DDC master,and CP Desire setting.\r
+ SWReset = HDMITX_ReadI2C_Byte(REG_TX_SW_RST);\r
+ CPDesire = HDMITX_ReadI2C_Byte(REG_TX_HDCP_DESIRE);\r
+ DDCMaster = HDMITX_ReadI2C_Byte(REG_TX_DDC_MASTER_CTRL);\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDCP_DESIRE,CPDesire&(~B_TX_CPDESIRE)); // @emily change order\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST,SWReset|B_TX_HDCP_RST_HDMITX); // @emily change order\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+\r
+ // 2009/01/15 modified by Jau-Chih.Tseng@ite.com.tw\r
+ // do abort DDC twice.\r
+ for( i = 0 ; i < 2 ; i++ )\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_DDC_ABORT);\r
+\r
+ for( timeout = 0 ; timeout < 200 ; timeout++ )\r
+ {\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+ if (uc&B_TX_DDC_DONE)\r
+ {\r
+ break ; // success\r
+ }\r
+ if( uc & (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE) )\r
+ {\r
+// HDMITX_DEBUG_PRINTF(("hdmitx_AbortDDC Fail by reg16=%02X\n",(int)uc));\r
+ break ;\r
+ }\r
+ delay1ms(1); // delay 1 ms to stable.\r
+ }\r
+ }\r
+ //~Jau-Chih.Tseng@ite.com.tw\r
+\r
+}\r
+\r
+///*****************************************\r
+// @file <hdmitx_vid.c>\r
+//******************************************/\r
+\r
+extern HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT] ;\r
+\r
+void WaitTxVidStable();\r
+void hdmitx_SetInputMode(BYTE InputMode,BYTE bInputSignalType);\r
+void hdmitx_SetCSCScale(BYTE bInputMode,BYTE bOutputMode);\r
+void hdmitx_SetupAFE(VIDEOPCLKLEVEL PCLKLevel);\r
+void hdmitx_FireAFE();\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// utility function for main..\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+#ifndef DISABLE_HDMITX_CSC\r
+ #if (defined (SUPPORT_OUTPUTYUV)) && (defined (SUPPORT_INPUTRGB))\r
+ extern _CODE BYTE bCSCMtx_RGB2YUV_ITU601_16_235[] ;\r
+ extern _CODE BYTE bCSCMtx_RGB2YUV_ITU601_0_255[] ;\r
+ extern _CODE BYTE bCSCMtx_RGB2YUV_ITU709_16_235[] ;\r
+ extern _CODE BYTE bCSCMtx_RGB2YUV_ITU709_0_255[] ;\r
+ #endif\r
+\r
+ #if (defined (SUPPORT_OUTPUTRGB)) && (defined (SUPPORT_INPUTYUV))\r
+ extern _CODE BYTE bCSCMtx_YUV2RGB_ITU601_16_235[] ;\r
+ extern _CODE BYTE bCSCMtx_YUV2RGB_ITU601_0_255[] ;\r
+ extern _CODE BYTE bCSCMtx_YUV2RGB_ITU709_16_235[] ;\r
+ extern _CODE BYTE bCSCMtx_YUV2RGB_ITU709_0_255[] ;\r
+\r
+ #endif\r
+#endif// DISABLE_HDMITX_CSC\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function Body.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void HDMITX_DisableVideoOutput()\r
+{\r
+ BYTE uc = HDMITX_ReadI2C_Byte(REG_TX_SW_RST) | B_HDMITX_VID_RST ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST,uc);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST|B_TX_AFE_DRV_PWD);\r
+ HDMITX_SetI2C_Byte(0x62, 0x90, 0x00);\r
+ HDMITX_SetI2C_Byte(0x64, 0x89, 0x00);\r
+}\r
+\r
+BOOL HDMITX_EnableVideoOutput(VIDEOPCLKLEVEL level,BYTE inputColorMode,BYTE outputColorMode,BYTE bHDMI)\r
+{\r
+ // bInputVideoMode,bOutputVideoMode,hdmiTxDev[0].bInputVideoSignalType,bAudioInputType,should be configured by upper F/W or loaded from EEPROM.\r
+ // should be configured by initsys.c\r
+ // VIDEOPCLKLEVEL level ;\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST,B_HDMITX_VID_RST|B_HDMITX_AUD_RST|B_TX_AREF_RST|B_TX_HDCP_RST_HDMITX);\r
+\r
+ hdmiTxDev[0].bHDMIMode = (BYTE)bHDMI ;\r
+ // 2009/12/09 added by jau-chih.tseng@ite.com.tw\r
+ Switch_HDMITX_Bank(1);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB1,0x00);\r
+ Switch_HDMITX_Bank(0);\r
+ //~jau-chih.tseng@ite.com.tw\r
+\r
+ if(hdmiTxDev[0].bHDMIMode)\r
+ {\r
+ setHDMITX_AVMute(TRUE);\r
+ }\r
+ hdmitx_SetInputMode(inputColorMode,hdmiTxDev[0].bInputVideoSignalType);\r
+\r
+ hdmitx_SetCSCScale(inputColorMode,outputColorMode);\r
+\r
+ if(hdmiTxDev[0].bHDMIMode)\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDMI_MODE,B_TX_HDMI_MODE);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDMI_MODE,B_TX_DVI_MODE);\r
+ }\r
+#ifdef INVERT_VID_LATCHEDGE\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1);\r
+ uc |= B_TX_VDO_LATCH_EDGE ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, uc);\r
+#endif\r
+\r
+ hdmitx_SetupAFE(level); // pass if High Freq request\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST, B_HDMITX_AUD_RST|B_TX_AREF_RST|B_TX_HDCP_RST_HDMITX);\r
+\r
+ hdmitx_FireAFE();\r
+\r
+ return TRUE ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// export this for dynamic change input signal\r
+//////////////////////////////////////////////////////////////////////\r
+BOOL setHDMITX_VideoSignalType(BYTE inputSignalType)\r
+{\r
+ hdmiTxDev[0].bInputVideoSignalType = inputSignalType ;\r
+ // hdmitx_SetInputMode(inputColorMode,hdmiTxDev[0].bInputVideoSignalType);\r
+ return TRUE ;\r
+}\r
+\r
+void WaitTxVidStable()\r
+{\r
+#if 0\r
+ BYTE i ;\r
+ for( i = 0 ; i < 20 ; i++ )\r
+ {\r
+ delay1ms(15);\r
+ if((HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS) & B_TXVIDSTABLE) == 0 )\r
+ {\r
+ continue ;\r
+ }\r
+ delay1ms(15);\r
+ if((HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS) & B_TXVIDSTABLE) == 0 )\r
+ {\r
+ continue ;\r
+ }\r
+ delay1ms(15);\r
+ if((HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS) & B_TXVIDSTABLE) == 0 )\r
+ {\r
+ continue ;\r
+ }\r
+ delay1ms(15);\r
+ if((HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS) & B_TXVIDSTABLE) == 0 )\r
+ {\r
+ continue ;\r
+ }\r
+ break ;\r
+ }\r
+#endif\r
+}\r
+// void CheckClockStable(BYTE SystemStat)\r
+// {\r
+// static BYTE Stablecnt=20;\r
+// if(0==(SystemStat&B_TXVIDSTABLE))\r
+// {\r
+// if(0==Stablecnt--)\r
+// {\r
+// HDMITX_ToggleBit(0x59,3);\r
+// Stablecnt=20;\r
+// }\r
+// }\r
+// else\r
+// {\r
+// Stablecnt=20;\r
+// }\r
+// }\r
+\r
+void setHDMITX_ColorDepthPhase(BYTE ColorDepth,BYTE bPhase)\r
+{\r
+#ifdef IT6615\r
+ BYTE uc ;\r
+ BYTE bColorDepth ;\r
+\r
+ if(ColorDepth == 30)\r
+ {\r
+ bColorDepth = B_TX_CD_30 ;\r
+ HDMITX_DEBUG_PRINTF(("bColorDepth = B_TX_CD_30\n"));\r
+ }\r
+ else if (ColorDepth == 36)\r
+ {\r
+ bColorDepth = B_TX_CD_36 ;\r
+ HDMITX_DEBUG_PRINTF(("bColorDepth = B_TX_CD_36\n"));\r
+ }\r
+ /*\r
+ else if (ColorDepth == 24)\r
+ {\r
+ bColorDepth = B_TX_CD_24 ;\r
+ //bColorDepth = 0 ;//modify JJ by mail 20100423 1800 // not indicated\r
+ }\r
+ */\r
+ else\r
+ {\r
+ bColorDepth = 0 ; // not indicated\r
+ }\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_SetI2C_Byte(REG_TX_GCP,B_TX_COLOR_DEPTH_MASK ,bColorDepth);\r
+ HDMITX_DEBUG_PRINTF(("setHDMITX_ColorDepthPhase(%02X), regC1 = %02X\n",(int)bColorDepth,(int)HDMITX_ReadI2C_Byte(REG_TX_GCP))) ;\r
+#endif\r
+}\r
+\r
+#ifdef SUPPORT_SYNCEMBEDDED\r
+\r
+struct CRT_TimingSetting {\r
+ BYTE fmt;\r
+ WORD HActive;\r
+ WORD VActive;\r
+ WORD HTotal;\r
+ WORD VTotal;\r
+ WORD H_FBH;\r
+ WORD H_SyncW;\r
+ WORD H_BBH;\r
+ WORD V_FBH;\r
+ WORD V_SyncW;\r
+ WORD V_BBH;\r
+ BYTE Scan:1;\r
+ BYTE VPolarity:1;\r
+ BYTE HPolarity:1;\r
+};\r
+\r
+// VDEE_L, VDEE_H, VRS2S_L, VRS2S_H, VRS2E_L, VRS2E_H, HalfL_L, HalfL_H, VDE2S_L, VDE2S_H, HVP&Progress\r
+_CODE struct CRT_TimingSetting TimingTable[] =\r
+{\r
+ // VIC H V HTotal VTotal HFT HSW HBP VF VSW VB\r
+ { 1, 640, 480, 800, 525, 16, 96, 48, 10, 2, 33, PROG, Vneg, Hneg},// 640x480@60Hz - CEA Mode [ 1]\r
+ { 2, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@60Hz - CEA Mode [ 2]\r
+ { 3, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@60Hz - CEA Mode [ 3]\r
+ { 4, 1280, 720, 1650, 750, 110, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@60Hz - CEA Mode [ 4]\r
+ { 5, 1920, 540, 2200, 562, 88, 44, 148, 2, 5, 15, INTERLACE, Vpos, Hpos},// 1920x1080(I)@60Hz - CEA Mode [ 5]\r
+ { 6, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [ 6]\r
+ { 7, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [ 7]\r
+ // { 8, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, PROG, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [ 8]\r
+ // { 9, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, PROG, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [ 9]\r
+ // { 10, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [10]\r
+ // { 11, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [11]\r
+ // { 12, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, PROG, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [12]\r
+ // { 13, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, PROG, Vneg, Hneg},// 720x480(I)@60Hz - CEA Mode [13]\r
+ // { 14, 1440, 480, 1716, 525, 32, 124, 120, 9, 6, 30, PROG, Vneg, Hneg},// 1440x480@60Hz - CEA Mode [14]\r
+ // { 15, 1440, 480, 1716, 525, 32, 124, 120, 9, 6, 30, PROG, Vneg, Hneg},// 1440x480@60Hz - CEA Mode [15]\r
+ { 16, 1920, 1080, 2200, 1125, 88, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@60Hz - CEA Mode [16]\r
+ { 17, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@50Hz - CEA Mode [17]\r
+ { 18, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@50Hz - CEA Mode [18]\r
+ { 19, 1280, 720, 1980, 750, 440, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@50Hz - CEA Mode [19]\r
+ { 20, 1920, 540, 2640, 562, 528, 44, 148, 2, 5, 15, INTERLACE, Vpos, Hpos},// 1920x1080(I)@50Hz - CEA Mode [20]\r
+ { 21, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@50Hz - CEA Mode [21]\r
+ { 22, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@50Hz - CEA Mode [22]\r
+ // { 23, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, PROG, Vneg, Hneg},// 1440x288@50Hz - CEA Mode [23]\r
+ // { 24, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, PROG, Vneg, Hneg},// 1440x288@50Hz - CEA Mode [24]\r
+ // { 25, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@50Hz - CEA Mode [25]\r
+ // { 26, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@50Hz - CEA Mode [26]\r
+ // { 27, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, PROG, Vneg, Hneg},// 1440x288@50Hz - CEA Mode [27]\r
+ // { 28, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, PROG, Vneg, Hneg},// 1440x288@50Hz - CEA Mode [28]\r
+ // { 29, 1440, 576, 1728, 625, 24, 128, 136, 5, 5, 39, PROG, Vpos, Hneg},// 1440x576@50Hz - CEA Mode [29]\r
+ // { 30, 1440, 576, 1728, 625, 24, 128, 136, 5, 5, 39, PROG, Vpos, Hneg},// 1440x576@50Hz - CEA Mode [30]\r
+ { 31, 1920, 1080, 2640, 1125, 528, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@50Hz - CEA Mode [31]\r
+ { 32, 1920, 1080, 2750, 1125, 638, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@24Hz - CEA Mode [32]\r
+ { 33, 1920, 1080, 2640, 1125, 528, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@25Hz - CEA Mode [33]\r
+ { 34, 1920, 1080, 2200, 1125, 88, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@30Hz - CEA Mode [34]\r
+ // { 35, 2880, 480, 1716*2, 525, 32*2, 124*2, 120*2, 9, 6, 30, PROG, Vneg, Hneg},// 2880x480@60Hz - CEA Mode [35]\r
+ // { 36, 2880, 480, 1716*2, 525, 32*2, 124*2, 120*2, 9, 6, 30, PROG, Vneg, Hneg},// 2880x480@60Hz - CEA Mode [36]\r
+ // { 37, 2880, 576, 3456, 625, 24*2, 128*2, 136*2, 5, 5, 39, PROG, Vneg, Hneg},// 2880x576@50Hz - CEA Mode [37]\r
+ // { 38, 2880, 576, 3456, 625, 24*2, 128*2, 136*2, 5, 5, 39, PROG, Vneg, Hneg},// 2880x576@50Hz - CEA Mode [38]\r
+ // { 39, 1920, 540, 2304, 625, 32, 168, 184, 23, 5, 57, INTERLACE, Vneg, Hpos},// 1920x1080@50Hz - CEA Mode [39]\r
+ // { 40, 1920, 540, 2640, 562, 528, 44, 148, 2, 5, 15, INTERLACE, Vpos, Hpos},// 1920x1080(I)@100Hz - CEA Mode [40]\r
+ // { 41, 1280, 720, 1980, 750, 440, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@100Hz - CEA Mode [41]\r
+ // { 42, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@100Hz - CEA Mode [42]\r
+ // { 43, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@100Hz - CEA Mode [43]\r
+ // { 44, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@100Hz - CEA Mode [44]\r
+ // { 45, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@100Hz - CEA Mode [45]\r
+ // { 46, 1920, 540, 2200, 562, 88, 44, 148, 2, 5, 15, INTERLACE, Vpos, Hpos},// 1920x1080(I)@120Hz - CEA Mode [46]\r
+ // { 47, 1280, 720, 1650, 750, 110, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@120Hz - CEA Mode [47]\r
+ // { 48, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@120Hz - CEA Mode [48]\r
+ // { 49, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@120Hz - CEA Mode [49]\r
+ // { 50, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@120Hz - CEA Mode [50]\r
+ // { 51, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@120Hz - CEA Mode [51]\r
+ // { 52, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@200Hz - CEA Mode [52]\r
+ // { 53, 720, 576, 864, 625, 12, 64, 68, 5, 5, 39, PROG, Vneg, Hneg},// 720x576@200Hz - CEA Mode [53]\r
+ // { 54, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@200Hz - CEA Mode [54]\r
+ // { 55, 720, 288, 864, 312, 12, 63, 69, 2, 3, 19, INTERLACE, Vneg, Hneg},// 1440x576(I)@200Hz - CEA Mode [55]\r
+ // { 56, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@120Hz - CEA Mode [56]\r
+ // { 57, 720, 480, 858, 525, 16, 62, 60, 9, 6, 30, PROG, Vneg, Hneg},// 720x480@120Hz - CEA Mode [57]\r
+ // { 58, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@120Hz - CEA Mode [58]\r
+ // { 59, 720, 240, 858, 262, 19, 62, 57, 4, 3, 15, INTERLACE, Vneg, Hneg},// 720x480(I)@120Hz - CEA Mode [59]\r
+ { 60, 1280, 720, 3300, 750, 1760, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@24Hz - CEA Mode [60]\r
+ { 61, 1280, 720, 3960, 750, 2420, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@25Hz - CEA Mode [61]\r
+ { 62, 1280, 720, 3300, 750, 1760, 40, 220, 5, 5, 20, PROG, Vpos, Hpos},// 1280x720@30Hz - CEA Mode [62]\r
+ // { 63, 1920, 1080, 2200, 1125, 88, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@120Hz - CEA Mode [63]\r
+ // { 64, 1920, 1080, 2640, 1125, 528, 44, 148, 4, 5, 36, PROG, Vpos, Hpos},// 1920x1080@100Hz - CEA Mode [64]\r
+};\r
+\r
+#define MaxIndex (sizeof(TimingTable)/sizeof(struct CRT_TimingSetting))\r
+BOOL setHDMITX_SyncEmbeddedByVIC(BYTE VIC,BYTE bInputType)\r
+{\r
+ int i ;\r
+ BYTE fmt_index=0;\r
+\r
+ // if Embedded Video,need to generate timing with pattern register\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ HDMITX_DEBUG_PRINTF(("setHDMITX_SyncEmbeddedByVIC(%d,%x)\n",(int)VIC,(int)bInputType));\r
+ if( VIC > 0 )\r
+ {\r
+ for(i=0;i< MaxIndex;i ++)\r
+ {\r
+ if(TimingTable[i].fmt==VIC)\r
+ {\r
+ fmt_index=i;\r
+ HDMITX_DEBUG_PRINTF(("fmt_index=%02x)\n",(int)fmt_index));\r
+ HDMITX_DEBUG_PRINTF(("***Fine Match Table ***\n"));\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("***No Match VIC == 0 ***\n"));\r
+ return FALSE ;\r
+ }\r
+\r
+ if(i>=MaxIndex)\r
+ {\r
+ //return FALSE;\r
+ HDMITX_DEBUG_PRINTF(("***No Match VIC ***\n"));\r
+ return FALSE ;\r
+ }\r
+ //if( bInputSignalType & T_MODE_SYNCEMB )\r
+ {\r
+ int HTotal, HDES, VTotal, VDES;\r
+ int HDEW, VDEW, HFP, HSW, VFP, VSW;\r
+ int HRS, HRE;\r
+ int VRS, VRE;\r
+ int H2ndVRRise;\r
+ int VRS2nd, VRE2nd;\r
+ BYTE Pol;\r
+\r
+ HTotal =TimingTable[fmt_index].HTotal;\r
+ HDEW =TimingTable[fmt_index].HActive;\r
+ HFP =TimingTable[fmt_index].H_FBH;\r
+ HSW =TimingTable[fmt_index].H_SyncW;\r
+ HDES =HSW+TimingTable[fmt_index].H_BBH;\r
+ VTotal =TimingTable[fmt_index].VTotal;\r
+ VDEW =TimingTable[fmt_index].VActive;\r
+ VFP =TimingTable[fmt_index].V_FBH;\r
+ VSW =TimingTable[fmt_index].V_SyncW;\r
+ VDES =VSW+TimingTable[fmt_index].V_BBH;\r
+\r
+ Pol = (TimingTable[fmt_index].HPolarity==Hpos)?(1<<1):0 ;\r
+ Pol |= (TimingTable[fmt_index].VPolarity==Vpos)?(1<<2):0 ;\r
+\r
+ // SyncEmb case=====\r
+ if( bInputType & T_MODE_CCIR656)\r
+ {\r
+ HRS = HFP - 1;\r
+ }\r
+ else\r
+ {\r
+ HRS = HFP - 2;\r
+ /*\r
+ if(VIC==HDMI_1080p60 ||\r
+ VIC==HDMI_1080p50 )\r
+ {\r
+ HDMITX_OrReg_Byte(0x59, (1<<3));\r
+ }\r
+ else\r
+ {\r
+ HDMITX_AndReg_Byte(0x59, ~(1<<3));\r
+ }\r
+ */\r
+ }\r
+ HRE = HRS + HSW;\r
+ H2ndVRRise = HRS+ HTotal/2;\r
+\r
+ VRS = VFP;\r
+ VRE = VRS + VSW;\r
+\r
+ // VTotal>>=1;\r
+\r
+ if(PROG == TimingTable[fmt_index].Scan)\r
+ { // progressive mode\r
+ VRS2nd = 0xFFF;\r
+ VRE2nd = 0x3F;\r
+ }\r
+ else\r
+ { // interlaced mode\r
+ if(39 == TimingTable[fmt_index].fmt)\r
+ {\r
+ VRS2nd = VRS + VTotal - 1;\r
+ VRE2nd = VRS2nd + VSW;\r
+ }\r
+ else\r
+ {\r
+ VRS2nd = VRS + VTotal;\r
+ VRE2nd = VRS2nd + VSW;\r
+ }\r
+ }\r
+ #ifdef DETECT_VSYNC_CHG_IN_SAV\r
+ if( EnSavVSync )\r
+ {\r
+ VRS -= 1;\r
+ VRE -= 1;\r
+ if( !pSetVTiming->ScanMode ) // interlaced mode\r
+ {\r
+ VRS2nd -= 1;\r
+ VRE2nd -= 1;\r
+ }\r
+ }\r
+ #endif // DETECT_VSYNC_CHG_IN_SAV\r
+ HDMITX_SetI2C_Byte(0x90, 0x06, Pol);\r
+ // write H2ndVRRise\r
+ HDMITX_SetI2C_Byte(0x90, 0xF0, (H2ndVRRise&0x0F)<<4);\r
+ HDMITX_WriteI2C_Byte(0x91, (H2ndVRRise&0x0FF0)>>4);\r
+ // write HRS/HRE\r
+ HDMITX_WriteI2C_Byte(0x95, HRS&0xFF);\r
+ HDMITX_WriteI2C_Byte(0x96, HRE&0xFF);\r
+ HDMITX_WriteI2C_Byte(0x97, ((HRE&0x0F00)>>4)+((HRS&0x0F00)>>8));\r
+ // write VRS/VRE\r
+ HDMITX_WriteI2C_Byte(0xa0, VRS&0xFF);\r
+ HDMITX_WriteI2C_Byte(0xa1, ((VRE&0x0F)<<4)+((VRS&0x0F00)>>8));\r
+ HDMITX_WriteI2C_Byte(0xa2, VRS2nd&0xFF);\r
+ HDMITX_WriteI2C_Byte(0xa6, (VRE2nd&0xF0)+((VRE&0xF0)>>4));\r
+ HDMITX_WriteI2C_Byte(0xa3, ((VRE2nd&0x0F)<<4)+((VRS2nd&0xF00)>>8));\r
+ HDMITX_WriteI2C_Byte(0xa4, H2ndVRRise&0xFF);\r
+ HDMITX_WriteI2C_Byte(0xa5, (/*EnDEOnly*/0<<5)+((TimingTable[fmt_index].Scan==INTERLACE)?(1<<4):0)+((H2ndVRRise&0xF00)>>8));\r
+ HDMITX_SetI2C_Byte(0xb1, 0x51, ((HRE&0x1000)>>6)+((HRS&0x1000)>>8)+((HDES&0x1000)>>12));\r
+ HDMITX_SetI2C_Byte(0xb2, 0x05, ((H2ndVRRise&0x1000)>>10)+((H2ndVRRise&0x1000)>>12));\r
+ }\r
+ return TRUE ;\r
+}\r
+\r
+#endif // SUPPORT_SYNCEMBEDDED\r
+\r
+//~jj_tseng@chipadvanced.com 2007/01/02\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetInputMode\r
+// Parameter: InputMode,bInputSignalType\r
+// InputMode - use [1:0] to identify the color space for reg70[7:6],\r
+// definition:\r
+// #define F_MODE_RGB444 0\r
+// #define F_MODE_YUV422 1\r
+// #define F_MODE_YUV444 2\r
+// #define F_MODE_CLRMOD_MASK 3\r
+// bInputSignalType - defined the CCIR656 D[0],SYNC Embedded D[1],and\r
+// DDR input in D[2].\r
+// Return: N/A\r
+// Remark: program Reg70 with the input value.\r
+// Side-Effect: Reg70.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_SetInputMode(BYTE InputColorMode,BYTE bInputSignalType)\r
+{\r
+ BYTE ucData ;\r
+\r
+ ucData = HDMITX_ReadI2C_Byte(REG_TX_INPUT_MODE);\r
+ ucData &= ~(M_TX_INCOLMOD|B_TX_2X656CLK|B_TX_SYNCEMB|B_TX_INDDR|B_TX_PCLKDIV2);\r
+ ucData |= 0x01;//input clock delay 1 for 1080P DDR\r
+\r
+ switch(InputColorMode & F_MODE_CLRMOD_MASK)\r
+ {\r
+ case F_MODE_YUV422:\r
+ ucData |= B_TX_IN_YUV422 ;\r
+ break ;\r
+ case F_MODE_YUV444:\r
+ ucData |= B_TX_IN_YUV444 ;\r
+ break ;\r
+ case F_MODE_RGB444:\r
+ default:\r
+ ucData |= B_TX_IN_RGB ;\r
+ break ;\r
+ }\r
+ if(bInputSignalType & T_MODE_PCLKDIV2)\r
+ {\r
+ ucData |= B_TX_PCLKDIV2 ; HDMITX_DEBUG_PRINTF(("PCLK Divided by 2 mode\n"));\r
+ }\r
+ if(bInputSignalType & T_MODE_CCIR656)\r
+ {\r
+ ucData |= B_TX_2X656CLK ; HDMITX_DEBUG_PRINTF(("CCIR656 mode\n"));\r
+ }\r
+ if(bInputSignalType & T_MODE_SYNCEMB)\r
+ {\r
+ ucData |= B_TX_SYNCEMB ; HDMITX_DEBUG_PRINTF(("Sync Embedded mode\n"));\r
+ }\r
+ if(bInputSignalType & T_MODE_INDDR)\r
+ {\r
+ ucData |= B_TX_INDDR ; HDMITX_DEBUG_PRINTF(("Input DDR mode\n"));\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_INPUT_MODE,ucData);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetCSCScale\r
+// Parameter: bInputMode -\r
+// D[1:0] - Color Mode\r
+// D[4] - Colorimetry 0: ITU_BT601 1: ITU_BT709\r
+// D[5] - Quantization 0: 0_255 1: 16_235\r
+// D[6] - Up/Dn Filter 'Required'\r
+// 0: no up/down filter\r
+// 1: enable up/down filter when csc need.\r
+// D[7] - Dither Filter 'Required'\r
+// 0: no dither enabled.\r
+// 1: enable dither and dither free go "when required".\r
+// bOutputMode -\r
+// D[1:0] - Color mode.\r
+// Return: N/A\r
+// Remark: reg72~reg8D will be programmed depended the input with table.\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_SetCSCScale(BYTE bInputMode,BYTE bOutputMode)\r
+{\r
+ BYTE ucData,csc ;\r
+ BYTE i ;\r
+ BYTE filter = 0 ; // filter is for Video CTRL DN_FREE_GO,EN_DITHER,and ENUDFILT\r
+\r
+ // (1) YUV422 in,RGB/YUV444 output (Output is 8-bit,input is 12-bit)\r
+ // (2) YUV444/422 in,RGB output (CSC enable,and output is not YUV422)\r
+ // (3) RGB in,YUV444 output (CSC enable,and output is not YUV422)\r
+ //\r
+ // YUV444/RGB24 <-> YUV422 need set up/down filter.\r
+ HDMITX_DEBUG_PRINTF(("hdmitx_SetCSCScale(BYTE bInputMode = %x,BYTE bOutputMode = %x)\n", (int)bInputMode, (int)bOutputMode)) ;\r
+ switch(bInputMode&F_MODE_CLRMOD_MASK)\r
+ {\r
+ #ifdef SUPPORT_INPUTYUV444\r
+ case F_MODE_YUV444:\r
+ HDMITX_DEBUG_PRINTF(("Input mode is YUV444 "));\r
+ switch(bOutputMode&F_MODE_CLRMOD_MASK)\r
+ {\r
+ case F_MODE_YUV444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV444\n"));\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+ break ;\r
+\r
+ case F_MODE_YUV422:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV422\n"));\r
+ if(bInputMode & F_VIDMODE_EN_UDFILT) // YUV444 to YUV422 need up/down filter for processing.\r
+ {\r
+ filter |= B_TX_EN_UDFILTER ;\r
+ }\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+ break ;\r
+ case F_MODE_RGB444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is RGB24\n"));\r
+ csc = B_HDMITX_CSC_YUV2RGB ;\r
+ if(bInputMode & F_VIDMODE_EN_DITHER) // YUV444 to RGB24 need dither\r
+ {\r
+ filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;\r
+ }\r
+ break ;\r
+ }\r
+ break ;\r
+ #endif\r
+\r
+ #ifdef SUPPORT_INPUTYUV422\r
+ case F_MODE_YUV422:\r
+ HDMITX_DEBUG_PRINTF(("Input mode is YUV422\n"));\r
+ switch(bOutputMode&F_MODE_CLRMOD_MASK)\r
+ {\r
+ case F_MODE_YUV444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV444\n"));\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+ if(bInputMode & F_VIDMODE_EN_UDFILT) // YUV422 to YUV444 need up filter\r
+ {\r
+ filter |= B_TX_EN_UDFILTER ;\r
+ }\r
+ if(bInputMode & F_VIDMODE_EN_DITHER) // YUV422 to YUV444 need dither\r
+ {\r
+ filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;\r
+ }\r
+ break ;\r
+ case F_MODE_YUV422:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV422\n"));\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+\r
+ break ;\r
+\r
+ case F_MODE_RGB444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is RGB24\n"));\r
+ csc = B_HDMITX_CSC_YUV2RGB ;\r
+ if(bInputMode & F_VIDMODE_EN_UDFILT) // YUV422 to RGB24 need up/dn filter.\r
+ {\r
+ filter |= B_TX_EN_UDFILTER ;\r
+ }\r
+ if(bInputMode & F_VIDMODE_EN_DITHER) // YUV422 to RGB24 need dither\r
+ {\r
+ filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;\r
+ }\r
+ break ;\r
+ }\r
+ break ;\r
+ #endif\r
+\r
+ #ifdef SUPPORT_INPUTRGB\r
+ case F_MODE_RGB444:\r
+ HDMITX_DEBUG_PRINTF(("Input mode is RGB24\n"));\r
+ switch(bOutputMode&F_MODE_CLRMOD_MASK)\r
+ {\r
+ case F_MODE_YUV444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV444\n"));\r
+ csc = B_HDMITX_CSC_RGB2YUV ;\r
+\r
+ if(bInputMode & F_VIDMODE_EN_DITHER) // RGB24 to YUV444 need dither\r
+ {\r
+ filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;\r
+ }\r
+ break ;\r
+\r
+ case F_MODE_YUV422:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is YUV422\n"));\r
+ if(bInputMode & F_VIDMODE_EN_UDFILT) // RGB24 to YUV422 need down filter.\r
+ {\r
+ filter |= B_TX_EN_UDFILTER ;\r
+ }\r
+ if(bInputMode & F_VIDMODE_EN_DITHER) // RGB24 to YUV422 need dither\r
+ {\r
+ filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;\r
+ }\r
+ csc = B_HDMITX_CSC_RGB2YUV ;\r
+ break ;\r
+\r
+ case F_MODE_RGB444:\r
+ HDMITX_DEBUG_PRINTF(("Output mode is RGB24\n"));\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+ break ;\r
+ }\r
+ break ;\r
+ #endif\r
+ }\r
+#ifndef DISABLE_HDMITX_CSC\r
+\r
+ #ifdef SUPPORT_INPUTRGB\r
+ // set the CSC metrix registers by colorimetry and quantization\r
+ if(csc == B_HDMITX_CSC_RGB2YUV)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("CSC = RGB2YUV %x ",csc));\r
+ switch(bInputMode&(F_VIDMODE_ITU709|F_VIDMODE_16_235))\r
+ {\r
+ case F_VIDMODE_ITU709|F_VIDMODE_16_235:\r
+ HDMITX_DEBUG_PRINTF(("ITU709 16-235 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU709_16_235[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU709_16_235[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU709|F_VIDMODE_0_255:\r
+ HDMITX_DEBUG_PRINTF(("ITU709 0-255 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU709_0_255[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU709_0_255[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU601|F_VIDMODE_16_235:\r
+ HDMITX_DEBUG_PRINTF(("ITU601 16-235 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU601_16_235[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU601_16_235[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU601|F_VIDMODE_0_255:\r
+ default:\r
+ HDMITX_DEBUG_PRINTF(("ITU601 0-255 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU601_0_255[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU601_0_255[i]));}\r
+ break ;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #ifdef SUPPORT_INPUTYUV\r
+ if (csc == B_HDMITX_CSC_YUV2RGB)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("CSC = YUV2RGB %x ",csc));\r
+\r
+ switch(bInputMode&(F_VIDMODE_ITU709|F_VIDMODE_16_235))\r
+ {\r
+ case F_VIDMODE_ITU709|F_VIDMODE_16_235:\r
+ HDMITX_DEBUG_PRINTF(("ITU709 16-235 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU709_16_235[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU709_16_235[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU709|F_VIDMODE_0_255:\r
+ HDMITX_DEBUG_PRINTF(("ITU709 0-255 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU709_0_255[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU709_0_255[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU601|F_VIDMODE_16_235:\r
+ HDMITX_DEBUG_PRINTF(("ITU601 16-235 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU601_16_235[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU601_16_235[i]));}\r
+ break ;\r
+ case F_VIDMODE_ITU601|F_VIDMODE_0_255:\r
+ default:\r
+ HDMITX_DEBUG_PRINTF(("ITU601 0-255 "));\r
+ for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ HDMITX_WriteI2C_Byte(REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU601_0_255[i]) ; HDMITX_DEBUG_PRINTF(("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU601_0_255[i]));}\r
+ break ;\r
+ }\r
+ }\r
+ #endif\r
+#else// DISABLE_HDMITX_CSC\r
+ csc = B_HDMITX_CSC_BYPASS ;\r
+#endif// DISABLE_HDMITX_CSC\r
+\r
+ if( csc == B_HDMITX_CSC_BYPASS )\r
+ {\r
+ HDMITX_SetI2C_Byte(0xF, 0x10, 0x10);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_SetI2C_Byte(0xF, 0x10, 0x00);\r
+ }\r
+ ucData = HDMITX_ReadI2C_Byte(REG_TX_CSC_CTRL) & ~(M_TX_CSC_SEL|B_TX_DNFREE_GO|B_TX_EN_DITHER|B_TX_EN_UDFILTER);\r
+ ucData |= filter|csc ;\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_CSC_CTRL,ucData);\r
+\r
+ // set output Up/Down Filter,Dither control\r
+\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetupAFE\r
+// Parameter: VIDEOPCLKLEVEL level\r
+// PCLK_LOW - for 13.5MHz (for mode less than 1080p)\r
+// PCLK MEDIUM - for 25MHz~74MHz\r
+// PCLK HIGH - PCLK > 80Hz (for 1080p mode or above)\r
+// Return: N/A\r
+// Remark: set reg62~reg65 depended on HighFreqMode\r
+// reg61 have to be programmed at last and after video stable input.\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_SetupAFE(VIDEOPCLKLEVEL level)\r
+{\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST);/* 0x10 */\r
+ switch(level)\r
+ {\r
+ case PCLK_HIGH:\r
+ HDMITX_SetI2C_Byte(0x62, 0x90, 0x80);\r
+ HDMITX_SetI2C_Byte(0x64, 0x89, 0x80);\r
+ HDMITX_SetI2C_Byte(0x68, 0x10, 0x80);\r
+ HDMITX_DEBUG_PRINTF(("hdmitx_SetupAFE()===================HIGHT\n"));\r
+ break ;\r
+ default:\r
+ HDMITX_SetI2C_Byte(0x62, 0x90, 0x10);\r
+ HDMITX_SetI2C_Byte(0x64, 0x89, 0x09);\r
+ HDMITX_SetI2C_Byte(0x68, 0x10, 0x10);\r
+ HDMITX_DEBUG_PRINTF(("hdmitx_SetupAFE()===================LOW\n"));\r
+ break ;\r
+ }\r
+ HDMITX_SetI2C_Byte(REG_TX_SW_RST,B_TX_REF_RST_HDMITX|B_HDMITX_VID_RST,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,0);\r
+ delay1ms(1);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_FireAFE\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: write reg61 with 0x04\r
+// When program reg61 with 0x04,then audio and video circuit work.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_FireAFE()\r
+{\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AFE_DRV_CTRL,0);\r
+}\r
+\r
+///*****************************************\r
+// @file <hdmitx_aud.c>\r
+//******************************************/\r
+\r
+BYTE AudioDelayCnt=0;\r
+BYTE LastRefaudfreqnum=0;\r
+BOOL bForceCTS = FALSE;\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Audio Output\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void setHDMITX_ChStat(BYTE ucIEC60958ChStat[])\r
+{\r
+ BYTE uc ;\r
+\r
+ Switch_HDMITX_Bank(1);\r
+ uc = (ucIEC60958ChStat[0] <<1)& 0x7C ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_MODE,uc);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CAT,ucIEC60958ChStat[1]); // 192, audio CATEGORY\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_SRCNUM,ucIEC60958ChStat[2]&0xF);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD0CHST_CHTNUM,(ucIEC60958ChStat[2]>>4)&0xF);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CA_FS,ucIEC60958ChStat[3]); // choose clock\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_OFS_WL,ucIEC60958ChStat[4]);\r
+ Switch_HDMITX_Bank(0);\r
+}\r
+\r
+void setHDMITX_UpdateChStatFs(ULONG Fs)\r
+{\r
+ BYTE uc ;\r
+\r
+ /////////////////////////////////////\r
+ // Fs should be the following value.\r
+ // #define AUDFS_22p05KHz 4\r
+ // #define AUDFS_44p1KHz 0\r
+ // #define AUDFS_88p2KHz 8\r
+ // #define AUDFS_176p4KHz 12\r
+ //\r
+ // #define AUDFS_24KHz 6\r
+ // #define AUDFS_48KHz 2\r
+ // #define AUDFS_96KHz 10\r
+ // #define AUDFS_192KHz 14\r
+ //\r
+ // #define AUDFS_768KHz 9\r
+ //\r
+ // #define AUDFS_32KHz 3\r
+ // #define AUDFS_OTHER 1\r
+ /////////////////////////////////////\r
+\r
+ Switch_HDMITX_Bank(1);\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_AUDCHST_CA_FS); // choose clock\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CA_FS,uc); // choose clock\r
+ uc &= 0xF0 ;\r
+ uc |= (Fs&0xF);\r
+\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_AUDCHST_OFS_WL);\r
+ uc &= 0xF ;\r
+ uc |= ((~Fs) << 4)&0xF0 ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_OFS_WL,uc);\r
+\r
+ Switch_HDMITX_Bank(0);\r
+}\r
+\r
+void setHDMITX_LPCMAudio(BYTE AudioSrcNum, BYTE AudSWL, BOOL bSPDIF)\r
+{\r
+\r
+ BYTE AudioEnable, AudioFormat ;\r
+\r
+ AudioEnable = 0 ;\r
+ AudioFormat = hdmiTxDev[0].bOutputAudioMode ;\r
+\r
+ switch(AudSWL)\r
+ {\r
+ case 16:\r
+ AudioEnable |= M_TX_AUD_16BIT ;\r
+ break ;\r
+ case 18:\r
+ AudioEnable |= M_TX_AUD_18BIT ;\r
+ break ;\r
+ case 20:\r
+ AudioEnable |= M_TX_AUD_20BIT ;\r
+ break ;\r
+ case 24:\r
+ default:\r
+ AudioEnable |= M_TX_AUD_24BIT ;\r
+ break ;\r
+ }\r
+ if( bSPDIF )\r
+ {\r
+ AudioFormat &= ~0x40 ;\r
+ AudioEnable |= B_TX_AUD_SPDIF|B_TX_AUD_EN_I2S0 ;\r
+ }\r
+ else\r
+ {\r
+ AudioFormat |= 0x40 ;\r
+ switch(AudioSrcNum)\r
+ {\r
+ case 4:\r
+ AudioEnable |= B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;\r
+ break ;\r
+\r
+ case 3:\r
+ AudioEnable |= B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;\r
+ break ;\r
+\r
+ case 2:\r
+ AudioEnable |= B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;\r
+ break ;\r
+\r
+ case 1:\r
+ default:\r
+ AudioFormat &= ~0x40 ;\r
+ AudioEnable |= B_TX_AUD_EN_I2S0 ;\r
+ break ;\r
+\r
+ }\r
+ }\r
+ AudioFormat|=0x01;//mingchih add\r
+ hdmiTxDev[0].bAudioChannelEnable=AudioEnable;\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0,AudioEnable&0xF0);\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL1,AudioFormat); // regE1 bOutputAudioMode should be loaded from ROM image.\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.\r
+#ifdef USE_SPDIF_CHSTAT\r
+ if( bSPDIF )\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,0);\r
+ }\r
+#else // not USE_SPDIF_CHSTAT\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,0);\r
+#endif // USE_SPDIF_CHSTAT\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,0x00);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ;\r
+\r
+ if( bSPDIF )\r
+ {\r
+ BYTE i ;\r
+ HDMITX_OrReg_Byte(0x5c,(1<<6));\r
+ for( i = 0 ; i < 100 ; i++ )\r
+ {\r
+ if(HDMITX_ReadI2C_Byte(REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)\r
+ {\r
+ break ; // stable clock.\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void setHDMITX_NLPCMAudio(BOOL bSPDIF) // no Source Num, no I2S.\r
+{\r
+ BYTE AudioEnable, AudioFormat ;\r
+ BYTE i ;\r
+\r
+ AudioFormat = 0x01 ; // NLPCM must use standard I2S mode.\r
+ if( bSPDIF )\r
+ {\r
+ AudioEnable = M_TX_AUD_24BIT|B_TX_AUD_SPDIF;\r
+ }\r
+ else\r
+ {\r
+ AudioEnable = M_TX_AUD_24BIT;\r
+ }\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ // HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, AudioEnable);\r
+ //HDMITX_AndREG_Byte(REG_TX_SW_RST,~(B_HDMITX_AUD_RST|B_TX_AREF_RST));\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL1,0x01); // regE1 bOutputAudioMode should be loaded from ROM image.\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.\r
+\r
+#ifdef USE_SPDIF_CHSTAT\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);\r
+#else // not USE_SPDIF_CHSTAT\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,0);\r
+#endif // USE_SPDIF_CHSTAT\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,0x00);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ;\r
+\r
+ if( bSPDIF )\r
+ {\r
+ for( i = 0 ; i < 100 ; i++ )\r
+ {\r
+ if(HDMITX_ReadI2C_Byte(REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)\r
+ {\r
+ break ; // stable clock.\r
+ }\r
+ }\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, AudioEnable|B_TX_AUD_EN_I2S0);\r
+}\r
+\r
+void setHDMITX_HBRAudio(BOOL bSPDIF)\r
+{\r
+ // BYTE rst;\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ // rst = HDMITX_ReadI2C_Byte(REG_TX_SW_RST);\r
+ // rst &= ~(B_HDMITX_AUD_RST|B_TX_AREF_RST);\r
+\r
+ // HDMITX_WriteI2C_Byte(REG_TX_SW_RST, rst | B_HDMITX_AUD_RST );\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL1,0x47); // regE1 bOutputAudioMode should be loaded from ROM image.\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.\r
+\r
+ if( bSPDIF )\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,0);\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,0x08);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_HDAUDIO,B_TX_HBR); // regE5 = 0 ;\r
+\r
+ //uc = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1);\r
+ //uc &= ~M_TX_AUD_DIV ;\r
+ //HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, uc);\r
+\r
+ if( bSPDIF )\r
+ {\r
+ BYTE i ;\r
+ for( i = 0 ; i < 100 ; i++ )\r
+ {\r
+ if(HDMITX_ReadI2C_Byte(REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)\r
+ {\r
+ break ; // stable clock.\r
+ }\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF|B_TX_AUD_EN_SPDIF);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0);\r
+ }\r
+ HDMITX_AndReg_Byte(0x5c,~(1<<6));\r
+ hdmiTxDev[0].bAudioChannelEnable=HDMITX_ReadI2C_Byte(REG_TX_AUDIO_CTRL0);\r
+ // HDMITX_WriteI2C_Byte(REG_TX_SW_RST, rst );\r
+}\r
+\r
+void setHDMITX_DSDAudio()\r
+{\r
+ // to be continue\r
+ // BYTE rst;\r
+ // rst = HDMITX_ReadI2C_Byte(REG_TX_SW_RST);\r
+\r
+ //HDMITX_WriteI2C_Byte(REG_TX_SW_RST, rst | (B_HDMITX_AUD_RST|B_TX_AREF_RST) );\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL1,0x41); // regE1 bOutputAudioMode should be loaded from ROM image.\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,0);\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,0x00);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_HDAUDIO,B_TX_DSD); // regE5 = 0 ;\r
+ //HDMITX_WriteI2C_Byte(REG_TX_SW_RST, rst & ~(B_HDMITX_AUD_RST|B_TX_AREF_RST) );\r
+\r
+ //uc = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1);\r
+ //uc &= ~M_TX_AUD_DIV ;\r
+ //HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, uc);\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0);\r
+}\r
+\r
+void HDMITX_DisableAudioOutput()\r
+{\r
+ //BYTE uc = (HDMITX_ReadI2C_Byte(REG_TX_SW_RST) | (B_HDMITX_AUD_RST | B_TX_AREF_RST));\r
+ //HDMITX_WriteI2C_Byte(REG_TX_SW_RST,uc);\r
+ AudioDelayCnt=AudioOutDelayCnt;\r
+ LastRefaudfreqnum=0;\r
+ HDMITX_SetI2C_Byte(REG_TX_SW_RST, (B_HDMITX_AUD_RST | B_TX_AREF_RST), (B_HDMITX_AUD_RST | B_TX_AREF_RST) );\r
+ HDMITX_SetI2C_Byte(0x0F, 0x10, 0x10 );\r
+}\r
+\r
+void HDMITX_EnableAudioOutput(BYTE AudioType, BOOL bSPDIF, ULONG SampleFreq, BYTE ChNum, BYTE *pIEC60958ChStat, ULONG TMDSClock)\r
+{\r
+ static _IDATA BYTE ucIEC60958ChStat[5] ;\r
+\r
+ BYTE Fs ;\r
+ AudioDelayCnt=36;\r
+ LastRefaudfreqnum=0;\r
+ hdmiTxDev[0].TMDSClock=TMDSClock;\r
+ hdmiTxDev[0].bAudioChannelEnable=0;\r
+ hdmiTxDev[0].bSPDIF_OUT=bSPDIF;\r
+\r
+ HDMITX_DEBUG_PRINTF1(("HDMITX_EnableAudioOutput(%02X, %s, %ld, %d, %p, %ld);\n",\r
+ AudioType, bSPDIF?"SPDIF":"I2S",SampleFreq, ChNum, pIEC60958ChStat, TMDSClock\r
+ ));\r
+\r
+ HDMITX_OrReg_Byte(REG_TX_SW_RST,(B_HDMITX_AUD_RST | B_TX_AREF_RST));\r
+ HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL0,B_TX_AUTO_OVER_SAMPLING_CLOCK|B_TX_EXT_256FS|0x01);\r
+\r
+ HDMITX_SetI2C_Byte(0x0F, 0x10, 0x00 ); // power on the ACLK\r
+\r
+ if(bSPDIF)\r
+ {\r
+ if(AudioType==T_AUDIO_HBR)\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL0,0x81);\r
+ }\r
+ HDMITX_OrReg_Byte(REG_TX_AUDIO_CTRL0,B_TX_AUD_SPDIF);\r
+ }\r
+ else\r
+ {\r
+ HDMITX_AndReg_Byte(REG_TX_AUDIO_CTRL0,(~B_TX_AUD_SPDIF));\r
+ }\r
+ if( AudioType != T_AUDIO_DSD)\r
+ {\r
+ // one bit audio have no channel status.\r
+ switch(SampleFreq)\r
+ {\r
+ case 44100L: Fs = AUDFS_44p1KHz ; break ;\r
+ case 88200L: Fs = AUDFS_88p2KHz ; break ;\r
+ case 176400L: Fs = AUDFS_176p4KHz ; break ;\r
+ case 32000L: Fs = AUDFS_32KHz ; break ;\r
+ case 48000L: Fs = AUDFS_48KHz ; break ;\r
+ case 96000L: Fs = AUDFS_96KHz ; break ;\r
+ case 192000L: Fs = AUDFS_192KHz ; break ;\r
+ case 768000L: Fs = AUDFS_768KHz ; break ;\r
+ default:\r
+ SampleFreq = 48000L ;\r
+ Fs = AUDFS_48KHz ;\r
+ break ; // default, set Fs = 48KHz.\r
+ }\r
+ #ifdef SUPPORT_AUDIO_MONITOR\r
+ hdmiTxDev[0].bAudFs=AUDFS_OTHER;\r
+ #else\r
+ hdmiTxDev[0].bAudFs=Fs;\r
+ #endif\r
+ setHDMITX_NCTS(hdmiTxDev[0].bAudFs);\r
+ if( pIEC60958ChStat == NULL )\r
+ {\r
+ ucIEC60958ChStat[0] = 0 ;\r
+ ucIEC60958ChStat[1] = 0 ;\r
+ ucIEC60958ChStat[2] = (ChNum+1)/2 ;\r
+\r
+ if(ucIEC60958ChStat[2]<1)\r
+ {\r
+ ucIEC60958ChStat[2] = 1 ;\r
+ }\r
+ else if( ucIEC60958ChStat[2] >4 )\r
+ {\r
+ ucIEC60958ChStat[2] = 4 ;\r
+ }\r
+ ucIEC60958ChStat[3] = Fs ;\r
+ ucIEC60958ChStat[4] = ((~Fs)<<4) & 0xF0 | CHTSTS_SWCODE ; // Fs | 24bit word length\r
+ pIEC60958ChStat = ucIEC60958ChStat ;\r
+ }\r
+ }\r
+ HDMITX_SetI2C_Byte(REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),B_TX_AREF_RST);\r
+\r
+ switch(AudioType)\r
+ {\r
+ case T_AUDIO_HBR:\r
+ HDMITX_DEBUG_PRINTF(("T_AUDIO_HBR\n"));\r
+ pIEC60958ChStat[0] |= 1<<1 ;\r
+ pIEC60958ChStat[2] = 0;\r
+ pIEC60958ChStat[3] &= 0xF0 ;\r
+ pIEC60958ChStat[3] |= AUDFS_768KHz ;\r
+ pIEC60958ChStat[4] |= (((~AUDFS_768KHz)<<4) & 0xF0)| 0xB ;\r
+ setHDMITX_ChStat(pIEC60958ChStat);\r
+ setHDMITX_HBRAudio(bSPDIF);\r
+\r
+ break ;\r
+ case T_AUDIO_DSD:\r
+ HDMITX_DEBUG_PRINTF(("T_AUDIO_DSD\n"));\r
+ setHDMITX_DSDAudio();\r
+ break ;\r
+ case T_AUDIO_NLPCM:\r
+ HDMITX_DEBUG_PRINTF(("T_AUDIO_NLPCM\n"));\r
+ pIEC60958ChStat[0] |= 1<<1 ;\r
+ setHDMITX_ChStat(pIEC60958ChStat);\r
+ setHDMITX_NLPCMAudio(bSPDIF);\r
+ break ;\r
+ case T_AUDIO_LPCM:\r
+ HDMITX_DEBUG_PRINTF(("T_AUDIO_LPCM\n"));\r
+ pIEC60958ChStat[0] &= ~(1<<1);\r
+\r
+ setHDMITX_ChStat(pIEC60958ChStat);\r
+ setHDMITX_LPCMAudio((ChNum+1)/2, SUPPORT_AUDI_AudSWL, bSPDIF);\r
+ // can add auto adjust\r
+ break ;\r
+ }\r
+ HDMITX_AndReg_Byte(REG_TX_INT_MASK1,(~B_TX_AUDIO_OVFLW_MASK));\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, hdmiTxDev[0].bAudioChannelEnable);\r
+\r
+ HDMITX_SetI2C_Byte(REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),0);\r
+}\r
+\r
+void hdmitx_AutoAdjustAudio()\r
+{\r
+ unsigned long SampleFreq,cTMDSClock ;\r
+ unsigned long N ;\r
+ ULONG aCTS=0;\r
+ BYTE fs, uc,LoopCnt=10;\r
+ if(bForceCTS)\r
+ {\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xC3);\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xA5);\r
+ HDMITX_AndReg_Byte(REG_TX_PKT_SINGLE_CTRL,~B_TX_SW_CTS); // D[1] = 0, HW auto count CTS\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xFF);\r
+ }\r
+ //delay1ms(50);\r
+ Switch_HDMITX_Bank(1);\r
+ N = ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudN2)&0xF) << 16 ;\r
+ N |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudN1)) <<8 ;\r
+ N |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudN0));\r
+\r
+ while(LoopCnt--)\r
+ { ULONG TempCTS=0;\r
+ aCTS = ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt2)) << 12 ;\r
+ aCTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt1)) <<4 ;\r
+ aCTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt0)&0xf0)>>4 ;\r
+ if(aCTS==TempCTS)\r
+ {break;}\r
+ TempCTS=aCTS;\r
+ }\r
+ Switch_HDMITX_Bank(0);\r
+ if( aCTS == 0)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("aCTS== 0"));\r
+ return;\r
+ }\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_GCP);\r
+\r
+ cTMDSClock = hdmiTxDev[0].TMDSClock ;\r
+ //TMDSClock=GetInputPclk();\r
+ HDMITX_DEBUG_PRINTF(("PCLK = %u0,000\n",(WORD)(cTMDSClock/10000)));\r
+ switch(uc & 0x70)\r
+ {\r
+ case 0x50:\r
+ cTMDSClock *= 5 ;\r
+ cTMDSClock /= 4 ;\r
+ break ;\r
+ case 0x60:\r
+ cTMDSClock *= 3 ;\r
+ cTMDSClock /= 2 ;\r
+ }\r
+ SampleFreq = cTMDSClock/aCTS ;\r
+ SampleFreq *= N ;\r
+ SampleFreq /= 128 ;\r
+ //SampleFreq=48000;\r
+\r
+ HDMITX_DEBUG_PRINTF(("SampleFreq = %u0\n",(WORD)(SampleFreq/10)));\r
+ if( SampleFreq>31000L && SampleFreq<=38050L ){fs = AUDFS_32KHz ;}\r
+ else if (SampleFreq < 46550L ) {fs = AUDFS_44p1KHz ;}//46050\r
+ else if (SampleFreq < 68100L ) {fs = AUDFS_48KHz ;}\r
+ else if (SampleFreq < 92100L ) {fs = AUDFS_88p2KHz ;}\r
+ else if (SampleFreq < 136200L ) {fs = AUDFS_96KHz ;}\r
+ else if (SampleFreq < 184200L ) {fs = AUDFS_176p4KHz ;}\r
+ else if (SampleFreq < 240200L ) {fs = AUDFS_192KHz ;}\r
+ else if (SampleFreq < 800000L ) {fs = AUDFS_768KHz ;}\r
+ else\r
+ {\r
+ fs = AUDFS_OTHER;\r
+ HDMITX_DEBUG_PRINTF(("fs = AUDFS_OTHER\n"));\r
+ }\r
+ if(hdmiTxDev[0].bAudFs != fs)\r
+ {\r
+ hdmiTxDev[0].bAudFs=fs;\r
+ setHDMITX_NCTS(hdmiTxDev[0].bAudFs); // set N, CTS by new generated clock.\r
+ //CurrCTS=0;\r
+ return;\r
+ }\r
+ return;\r
+}\r
+\r
+BOOL hdmitx_IsAudioChang()\r
+{\r
+ //ULONG pCTS=0;\r
+ BYTE FreDiff=0,Refaudfreqnum;\r
+\r
+ //Switch_HDMITX_Bank(1);\r
+ //pCTS = ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt2)) << 12 ;\r
+ //pCTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt1)) <<4 ;\r
+ //pCTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt0)&0xf0)>>4 ;\r
+ //Switch_HDMITX_Bank(0);\r
+ Switch_HDMITX_Bank(0);\r
+ Refaudfreqnum=HDMITX_ReadI2C_Byte(0x60);\r
+ //HDMITX_DEBUG_PRINTF(("Refaudfreqnum=%X pCTS= %u",(WORD)Refaudfreqnum,(WORD)(pCTS/10000)));\r
+ //if((pCTS%10000)<1000)HDMITX_DEBUG_PRINTF(("0"));\r
+ //if((pCTS%10000)<100)HDMITX_DEBUG_PRINTF(("0"));\r
+ //if((pCTS%10000)<10)HDMITX_DEBUG_PRINTF(("0"));\r
+ //HDMITX_DEBUG_PRINTF(("%u\n",(WORD)(pCTS%10000)));\r
+ if((1<<4)&HDMITX_ReadI2C_Byte(0x5f))\r
+ {\r
+ //printf("=======XXXXXXXXXXX=========\n");\r
+ return FALSE;\r
+ }\r
+ if(LastRefaudfreqnum>Refaudfreqnum)\r
+ {FreDiff=LastRefaudfreqnum-Refaudfreqnum;}\r
+ else\r
+ {FreDiff=Refaudfreqnum-LastRefaudfreqnum;}\r
+ LastRefaudfreqnum=Refaudfreqnum;\r
+ if(3<FreDiff)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("Aduio FreDiff=%d\n",(int)FreDiff));\r
+ HDMITX_OrReg_Byte(REG_TX_PKT_SINGLE_CTRL,(1<<5));\r
+ HDMITX_AndReg_Byte(REG_TX_AUDIO_CTRL0,0xF0);\r
+ return TRUE;\r
+ }\r
+ else\r
+ {\r
+ return FALSE;\r
+ }\r
+}\r
+\r
+void setHDMITX_AudioChannelEnable(BOOL EnableAudio_b)\r
+{\r
+ static BOOL AudioOutStatus=FALSE;\r
+ if(EnableAudio_b)\r
+ {\r
+ if(AudioDelayCnt==0)\r
+ {\r
+ //if(hdmiTxDev[0].bAuthenticated==FALSE)\r
+ //{HDMITX_EnableHDCP(TRUE);}\r
+ #ifdef SUPPORT_AUDIO_MONITOR\r
+ if(hdmitx_IsAudioChang())\r
+ {\r
+ hdmitx_AutoAdjustAudio();\r
+ #else\r
+ if(AudioOutStatus==FALSE)\r
+ {\r
+ setHDMITX_NCTS(hdmiTxDev[0].bAudFs);\r
+ #endif\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,0);\r
+ HDMITX_OrReg_Byte(REG_TX_PKT_SINGLE_CTRL,(1<<5));\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL0, hdmiTxDev[0].bAudioChannelEnable);\r
+ //HDMITX_OrREG_Byte(0x59,(1<<2)); //for test\r
+ HDMITX_AndReg_Byte(REG_TX_PKT_SINGLE_CTRL,(~0x3C));\r
+ HDMITX_AndReg_Byte(REG_TX_PKT_SINGLE_CTRL,(~(1<<5)));\r
+ printk("Audio Out Enable\n");\r
+ #ifndef SUPPORT_AUDIO_MONITOR\r
+ AudioOutStatus=TRUE;\r
+ #endif\r
+ }\r
+ }\r
+ else\r
+ {\r
+ AudioOutStatus=FALSE;\r
+ if(0==(HDMITX_ReadI2C_Byte(REG_TX_CLK_STATUS2)&0x10))\r
+ {\r
+ AudioDelayCnt--;\r
+ }\r
+ else\r
+ {\r
+ AudioDelayCnt=AudioOutDelayCnt;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // CurrCTS=0;\r
+ }\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: setHDMITX_NCTS\r
+// Parameter: PCLK - video clock in Hz.\r
+// Fs - Encoded audio sample rate\r
+// AUDFS_22p05KHz 4\r
+// AUDFS_44p1KHz 0\r
+// AUDFS_88p2KHz 8\r
+// AUDFS_176p4KHz 12\r
+//\r
+// AUDFS_24KHz 6\r
+// AUDFS_48KHz 2\r
+// AUDFS_96KHz 10\r
+// AUDFS_192KHz 14\r
+//\r
+// AUDFS_768KHz 9\r
+//\r
+// AUDFS_32KHz 3\r
+// AUDFS_OTHER 1\r
+// Return: ER_SUCCESS if success\r
+// Remark: set N value,the CTS will be auto generated by HW.\r
+// Side-Effect: register bank will reset to bank 0.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void setHDMITX_NCTS(BYTE Fs)\r
+{\r
+ ULONG n;\r
+ BYTE LoopCnt=255,CTSStableCnt=0;\r
+ ULONG diff;\r
+ ULONG CTS=0,LastCTS=0;\r
+ BOOL HBR_mode;\r
+ // BYTE aVIC;\r
+\r
+ if(B_TX_HBR & HDMITX_ReadI2C_Byte(REG_TX_AUD_HDAUDIO))\r
+ {\r
+ HBR_mode=TRUE;\r
+ }\r
+ else\r
+ {\r
+ HBR_mode=FALSE;\r
+ }\r
+ switch(Fs)\r
+ {\r
+ case AUDFS_32KHz: n = 4096; break;\r
+ case AUDFS_44p1KHz: n = 6272; break;\r
+ case AUDFS_48KHz: n = 6144; break;\r
+ case AUDFS_88p2KHz: n = 12544; break;\r
+ case AUDFS_96KHz: n = 12288; break;\r
+ case AUDFS_176p4KHz: n = 25088; break;\r
+ case AUDFS_192KHz: n = 24576; break;\r
+ case AUDFS_768KHz: n = 24576; break ;\r
+ default: n = 6144;\r
+ }\r
+ // tr_printf((" n = %ld\n",n));\r
+ Switch_HDMITX_Bank(1);\r
+ HDMITX_WriteI2C_Byte(REGPktAudN0,(BYTE)((n)&0xFF));\r
+ HDMITX_WriteI2C_Byte(REGPktAudN1,(BYTE)((n>>8)&0xFF));\r
+ HDMITX_WriteI2C_Byte(REGPktAudN2,(BYTE)((n>>16)&0xF));\r
+\r
+ if(bForceCTS)\r
+ {\r
+ ULONG SumCTS=0;\r
+ while(LoopCnt--)\r
+ {\r
+ delay1ms(30);\r
+ CTS = ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt2)) << 12 ;\r
+ CTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt1)) <<4 ;\r
+ CTS |= ((unsigned long)HDMITX_ReadI2C_Byte(REGPktAudCTSCnt0)&0xf0)>>4 ;\r
+ if( CTS == 0)\r
+ {\r
+ continue;\r
+ }\r
+ else\r
+ {\r
+ if(LastCTS>CTS )\r
+ {diff=LastCTS-CTS;}\r
+ else\r
+ {diff=CTS-LastCTS;}\r
+ //HDMITX_DEBUG_PRINTF(("LastCTS= %u%u",(WORD)(LastCTS/10000),(WORD)(LastCTS%10000)));\r
+ //HDMITX_DEBUG_PRINTF((" CTS= %u%u\n",(WORD)(CTS/10000),(WORD)(CTS%10000)));\r
+ LastCTS=CTS;\r
+ if(5>diff)\r
+ {\r
+ CTSStableCnt++;\r
+ SumCTS+=CTS;\r
+ }\r
+ else\r
+ {\r
+ CTSStableCnt=0;\r
+ SumCTS=0;\r
+ continue;\r
+ }\r
+ if(CTSStableCnt>=32)\r
+ {\r
+ LastCTS=(SumCTS>>5);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ HDMITX_WriteI2C_Byte(REGPktAudCTS0,(BYTE)((LastCTS)&0xFF));\r
+ HDMITX_WriteI2C_Byte(REGPktAudCTS1,(BYTE)((LastCTS>>8)&0xFF));\r
+ HDMITX_WriteI2C_Byte(REGPktAudCTS2,(BYTE)((LastCTS>>16)&0xF));\r
+ Switch_HDMITX_Bank(0);\r
+#ifdef Force_CTS\r
+ bForceCTS = TRUE;\r
+#endif\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xC3);\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xA5);\r
+ if(bForceCTS)\r
+ {\r
+ HDMITX_OrReg_Byte(REG_TX_PKT_SINGLE_CTRL,B_TX_SW_CTS); // D[1] = 0, HW auto count CTS\r
+ }\r
+ else\r
+ {\r
+ HDMITX_AndReg_Byte(REG_TX_PKT_SINGLE_CTRL,~B_TX_SW_CTS); // D[1] = 0, HW auto count CTS\r
+ }\r
+ HDMITX_WriteI2C_Byte(0xF8, 0xFF);\r
+\r
+ if(FALSE==HBR_mode) //LPCM\r
+ {\r
+ BYTE uData;\r
+ Switch_HDMITX_Bank(1);\r
+ Fs = AUDFS_768KHz ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CA_FS,0x00|Fs);\r
+ Fs = ~Fs ; // OFS is the one's complement of FS\r
+ uData = (0x0f&HDMITX_ReadI2C_Byte(REG_TX_AUDCHST_OFS_WL));\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_OFS_WL,(Fs<<4)|uData);\r
+ Switch_HDMITX_Bank(0);\r
+ }\r
+}\r
+\r
+///*****************************************\r
+// @file <hdmitx_pkt.c>\r
+//******************************************/\r
+\r
+BOOL HDMITX_EnableVSInfoFrame(BYTE bEnable,BYTE *pVSInfoFrame)\r
+{\r
+ if(!bEnable)\r
+ {\r
+ hdmitx_DISABLE_VSDB_PKT();\r
+ return TRUE ;\r
+ }\r
+ if(hdmitx_SetVSIInfoFrame((VendorSpecific_InfoFrame *)pVSInfoFrame) == ER_SUCCESS)\r
+ {\r
+ return TRUE ;\r
+ }\r
+ return FALSE ;\r
+}\r
+\r
+BOOL HDMITX_EnableAVIInfoFrame(BYTE bEnable,BYTE *pAVIInfoFrame)\r
+{\r
+ if(!bEnable)\r
+ {\r
+ hdmitx_DISABLE_AVI_INFOFRM_PKT();\r
+ return TRUE ;\r
+ }\r
+ if(hdmitx_SetAVIInfoFrame((AVI_InfoFrame *)pAVIInfoFrame) == ER_SUCCESS)\r
+ {\r
+ return TRUE ;\r
+ }\r
+ return FALSE ;\r
+}\r
+\r
+BOOL HDMITX_EnableAudioInfoFrame(BYTE bEnable,BYTE *pAudioInfoFrame)\r
+{\r
+ if(!bEnable)\r
+ {\r
+ hdmitx_DISABLE_AVI_INFOFRM_PKT();\r
+ return TRUE ;\r
+ }\r
+ if(hdmitx_SetAudioInfoFrame((Audio_InfoFrame *)pAudioInfoFrame) == ER_SUCCESS)\r
+ {\r
+ return TRUE ;\r
+ }\r
+ return FALSE ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetAVIInfoFrame()\r
+// Parameter: pAVIInfoFrame - the pointer to HDMI AVI Infoframe ucData\r
+// Return: N/A\r
+// Remark: Fill the AVI InfoFrame ucData,and count checksum,then fill into\r
+// AVI InfoFrame registers.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_SetAVIInfoFrame(AVI_InfoFrame *pAVIInfoFrame)\r
+{\r
+ int i ;\r
+ byte checksum ;\r
+\r
+ if(!pAVIInfoFrame)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB1,pAVIInfoFrame->pktbyte.AVI_DB[0]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB2,pAVIInfoFrame->pktbyte.AVI_DB[1]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB3,pAVIInfoFrame->pktbyte.AVI_DB[2]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB4,pAVIInfoFrame->pktbyte.AVI_DB[3]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB5,pAVIInfoFrame->pktbyte.AVI_DB[4]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB6,pAVIInfoFrame->pktbyte.AVI_DB[5]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB7,pAVIInfoFrame->pktbyte.AVI_DB[6]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB8,pAVIInfoFrame->pktbyte.AVI_DB[7]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB9,pAVIInfoFrame->pktbyte.AVI_DB[8]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB10,pAVIInfoFrame->pktbyte.AVI_DB[9]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB11,pAVIInfoFrame->pktbyte.AVI_DB[10]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB12,pAVIInfoFrame->pktbyte.AVI_DB[11]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB13,pAVIInfoFrame->pktbyte.AVI_DB[12]);\r
+ for(i = 0,checksum = 0; i < 13 ; i++)\r
+ {\r
+ checksum -= pAVIInfoFrame->pktbyte.AVI_DB[i] ;\r
+ }\r
+ /*\r
+ HDMITX_DEBUG_PRINTF(("SetAVIInfo(): "));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB1)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB2)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB3)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB4)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB5)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB6)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB7)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB8)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB9)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB10)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB11)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB12)));\r
+ HDMITX_DEBUG_PRINTF(("%02X ",(int)HDMITX_ReadI2C_Byte(REG_TX_AVIINFO_DB13)));\r
+ HDMITX_DEBUG_PRINTF(("\n"));\r
+ */\r
+ checksum -= AVI_INFOFRAME_VER+AVI_INFOFRAME_TYPE+AVI_INFOFRAME_LEN ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_SUM,checksum);\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ hdmitx_ENABLE_AVI_INFOFRM_PKT();\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetAudioInfoFrame()\r
+// Parameter: pAudioInfoFrame - the pointer to HDMI Audio Infoframe ucData\r
+// Return: N/A\r
+// Remark: Fill the Audio InfoFrame ucData,and count checksum,then fill into\r
+// Audio InfoFrame registers.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_SetAudioInfoFrame(Audio_InfoFrame *pAudioInfoFrame)\r
+{\r
+ BYTE checksum ;\r
+\r
+ if(!pAudioInfoFrame)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+ checksum = 0x100-(AUDIO_INFOFRAME_VER+AUDIO_INFOFRAME_TYPE+AUDIO_INFOFRAME_LEN );\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_AUDINFO_CC,pAudioInfoFrame->pktbyte.AUD_DB[0]);\r
+ checksum -= HDMITX_ReadI2C_Byte(REG_TX_PKT_AUDINFO_CC); checksum &= 0xFF ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_AUDINFO_SF,pAudioInfoFrame->pktbyte.AUD_DB[1]);\r
+ checksum -= HDMITX_ReadI2C_Byte(REG_TX_PKT_AUDINFO_SF); checksum &= 0xFF ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_AUDINFO_CA,pAudioInfoFrame->pktbyte.AUD_DB[3]);\r
+ checksum -= HDMITX_ReadI2C_Byte(REG_TX_PKT_AUDINFO_CA); checksum &= 0xFF ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_AUDINFO_DM_LSV,pAudioInfoFrame->pktbyte.AUD_DB[4]);\r
+ checksum -= HDMITX_ReadI2C_Byte(REG_TX_PKT_AUDINFO_DM_LSV); checksum &= 0xFF ;\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_AUDINFO_SUM,checksum);\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ hdmitx_ENABLE_AUD_INFOFRM_PKT();\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetSPDInfoFrame()\r
+// Parameter: pSPDInfoFrame - the pointer to HDMI SPD Infoframe ucData\r
+// Return: N/A\r
+// Remark: Fill the SPD InfoFrame ucData,and count checksum,then fill into\r
+// SPD InfoFrame registers.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_SetSPDInfoFrame(SPD_InfoFrame *pSPDInfoFrame)\r
+{\r
+ int i ;\r
+ BYTE ucData ;\r
+\r
+ if(!pSPDInfoFrame)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+ for(i = 0,ucData = 0 ; i < 25 ; i++)\r
+ {\r
+ ucData -= pSPDInfoFrame->pktbyte.SPD_DB[i] ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_SPDINFO_PB1+i,pSPDInfoFrame->pktbyte.SPD_DB[i]);\r
+ }\r
+ ucData -= SPD_INFOFRAME_VER+SPD_INFOFRAME_TYPE+SPD_INFOFRAME_LEN ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_SPDINFO_SUM,ucData); // checksum\r
+ Switch_HDMITX_Bank(0);\r
+ hdmitx_ENABLE_SPD_INFOFRM_PKT();\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_SetMPEGInfoFrame()\r
+// Parameter: pMPEGInfoFrame - the pointer to HDMI MPEG Infoframe ucData\r
+// Return: N/A\r
+// Remark: Fill the MPEG InfoFrame ucData,and count checksum,then fill into\r
+// MPEG InfoFrame registers.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_SetMPEGInfoFrame(MPEG_InfoFrame *pMPGInfoFrame)\r
+{\r
+ int i ;\r
+ BYTE ucData ;\r
+\r
+ if(!pMPGInfoFrame)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKT_MPGINFO_FMT,pMPGInfoFrame->info.FieldRepeat|(pMPGInfoFrame->info.MpegFrame<<1));\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKG_MPGINFO_DB0,pMPGInfoFrame->pktbyte.MPG_DB[0]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKG_MPGINFO_DB1,pMPGInfoFrame->pktbyte.MPG_DB[1]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKG_MPGINFO_DB2,pMPGInfoFrame->pktbyte.MPG_DB[2]);\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKG_MPGINFO_DB3,pMPGInfoFrame->pktbyte.MPG_DB[3]);\r
+\r
+ for(ucData = 0,i = 0 ; i < 5 ; i++)\r
+ {\r
+ ucData -= pMPGInfoFrame->pktbyte.MPG_DB[i] ;\r
+ }\r
+ ucData -= MPEG_INFOFRAME_VER+MPEG_INFOFRAME_TYPE+MPEG_INFOFRAME_LEN ;\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_PKG_MPGINFO_SUM,ucData);\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ hdmitx_ENABLE_SPD_INFOFRM_PKT();\r
+\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+// 2009/12/04 added by Ming-chih.lung@ite.com.tw\r
+\r
+SYS_STATUS hdmitx_SetVSIInfoFrame(VendorSpecific_InfoFrame *pVSIInfoFrame)\r
+{\r
+ BYTE ucData=0 ;\r
+\r
+ if(!pVSIInfoFrame)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+\r
+ Switch_HDMITX_Bank(1);\r
+ HDMITX_WriteI2C_Byte(0x80,pVSIInfoFrame->pktbyte.VS_DB[3]);\r
+ HDMITX_WriteI2C_Byte(0x81,pVSIInfoFrame->pktbyte.VS_DB[4]);\r
+\r
+ ucData -= pVSIInfoFrame->pktbyte.VS_DB[3] ;\r
+ ucData -= pVSIInfoFrame->pktbyte.VS_DB[4] ;\r
+\r
+ if( pVSIInfoFrame->pktbyte.VS_DB[4] & (1<<7 ))\r
+ {\r
+ ucData -= pVSIInfoFrame->pktbyte.VS_DB[5] ;\r
+ HDMITX_WriteI2C_Byte(0x82,pVSIInfoFrame->pktbyte.VS_DB[5]);\r
+ ucData -= VENDORSPEC_INFOFRAME_TYPE + VENDORSPEC_INFOFRAME_VER + 6 + 0x0C + 0x03 ;\r
+ }\r
+ else\r
+ {\r
+ ucData -= VENDORSPEC_INFOFRAME_TYPE + VENDORSPEC_INFOFRAME_VER + 5 + 0x0C + 0x03 ;\r
+ }\r
+\r
+ pVSIInfoFrame->pktbyte.CheckSum=ucData;\r
+\r
+ HDMITX_WriteI2C_Byte(0x83,pVSIInfoFrame->pktbyte.CheckSum);\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_3D_INFO_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT);\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+SYS_STATUS hdmitx_Set_GeneralPurpose_PKT(BYTE *pData)\r
+{\r
+ int i ;\r
+\r
+ if( pData == NULL )\r
+ {\r
+ return ER_FAIL ;\r
+\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+ for( i = 0x38 ; i <= 0x56 ; i++)\r
+ {\r
+ HDMITX_WriteI2C_Byte(i, pData[i-0x38] );\r
+ }\r
+ Switch_HDMITX_Bank(0);\r
+ hdmitx_ENABLE_GeneralPurpose_PKT();\r
+ //hdmitx_ENABLE_NULL_PKT();\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: DumpHDMITXReg()\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: Debug function,dumps the registers of CAT6611.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+#if Debug_message\r
+void DumpHDMITXReg()\r
+{\r
+ int i,j ;\r
+ BYTE ucData ;\r
+\r
+ HDMITX_DEBUG_PRINTF((" "));\r
+ for(j = 0 ; j < 16 ; j++)\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" %02X",(int)j));\r
+ if((j == 3)||(j==7)||(j==11))\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" "));\r
+ }\r
+ }\r
+ HDMITX_DEBUG_PRINTF(("\n -----------------------------------------------------\n"));\r
+\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ for(i = 0 ; i < 0x100 ; i+=16)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("[%3X] ",i));\r
+ for(j = 0 ; j < 16 ; j++)\r
+ {\r
+ if( (i+j)!= 0x17)\r
+ {\r
+ ucData = HDMITX_ReadI2C_Byte((BYTE)((i+j)&0xFF));\r
+ HDMITX_DEBUG_PRINTF((" %02X",(int)ucData));\r
+ }\r
+ else\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" XX",(int)ucData)); // for DDC FIFO\r
+ }\r
+ if((j == 3)||(j==7)||(j==11))\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" -"));\r
+ }\r
+ }\r
+ HDMITX_DEBUG_PRINTF(("\n"));\r
+ if((i % 0x40) == 0x30)\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" -----------------------------------------------------\n"));\r
+ }\r
+ }\r
+ Switch_HDMITX_Bank(1);\r
+ for(i = 0x130; i < 0x200 ; i+=16)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("[%3X] ",i));\r
+ for(j = 0 ; j < 16 ; j++)\r
+ {\r
+ ucData = HDMITX_ReadI2C_Byte((BYTE)((i+j)&0xFF));\r
+ HDMITX_DEBUG_PRINTF((" %02X",(int)ucData));\r
+ if((j == 3)||(j==7)||(j==11))\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" -"));\r
+ }\r
+ }\r
+ HDMITX_DEBUG_PRINTF(("\n"));\r
+ if((i % 0x40) == 0x20)\r
+ {\r
+ HDMITX_DEBUG_PRINTF((" -----------------------------------------------------\n"));\r
+ }\r
+ }\r
+ HDMITX_DEBUG_PRINTF((" -----------------------------------------------------\n"));\r
+ Switch_HDMITX_Bank(0);\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_drv.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+#ifndef _HDMITX_DRV_H_\r
+#define _HDMITX_DRV_H_\r
+\r
+//#define EXTERN_HDCPROM\r
+/////////////////////////////////////////\r
+// DDC Address\r
+/////////////////////////////////////////\r
+#define DDC_HDCP_ADDRESS 0x74\r
+#define DDC_EDID_ADDRESS 0xA0\r
+#define DDC_FIFO_MAXREQ 0x20\r
+\r
+// I2C address\r
+\r
+#define _80MHz 80000000\r
+#define HDMI_TX_I2C_SLAVE_ADDR 0x98\r
+#define CEC_I2C_SLAVE_ADDR 0x9C\r
+\r
+#define DISABLE_HDMITX_CSC\r
+///////////////////////////////////////////////////////////////////////\r
+// Register offset\r
+///////////////////////////////////////////////////////////////////////\r
+\r
+#define REG_TX_VENDOR_ID0 0x00\r
+#define REG_TX_VENDOR_ID1 0x01\r
+#define REG_TX_DEVICE_ID0 0x02\r
+#define REG_TX_DEVICE_ID1 0x03\r
+\r
+ #define O_TX_DEVID 0\r
+ #define M_TX_DEVID 0xF\r
+ #define O_TX_REVID 4\r
+ #define M_TX_REVID 0xF\r
+\r
+#define REG_TX_SW_RST 0x04\r
+ #define B_TX_ENTEST (1<<7)\r
+ #define B_TX_REF_RST_HDMITX (1<<5)\r
+ #define B_TX_AREF_RST (1<<4)\r
+ #define B_HDMITX_VID_RST (1<<3)\r
+ #define B_HDMITX_AUD_RST (1<<2)\r
+ #define B_TX_HDMI_RST (1<<1)\r
+ #define B_TX_HDCP_RST_HDMITX (1<<0)\r
+\r
+#define REG_TX_INT_CTRL 0x05\r
+ #define B_TX_INTPOL_ACTL 0\r
+ #define B_TX_INTPOL_ACTH (1<<7)\r
+ #define B_TX_INT_PUSHPULL 0\r
+ #define B_TX_INT_OPENDRAIN (1<<6)\r
+\r
+#define REG_TX_INT_STAT1 0x06\r
+ #define B_TX_INT_AUD_OVERFLOW (1<<7)\r
+ #define B_TX_INT_ROMACQ_NOACK (1<<6)\r
+ #define B_TX_INT_RDDC_NOACK (1<<5)\r
+ #define B_TX_INT_DDCFIFO_ERR (1<<4)\r
+ #define B_TX_INT_ROMACQ_BUS_HANG (1<<3)\r
+ #define B_TX_INT_DDC_BUS_HANG (1<<2)\r
+ #define B_TX_INT_RX_SENSE (1<<1)\r
+ #define B_TX_INT_HPD_PLUG (1<<0)\r
+\r
+#define REG_TX_INT_STAT2 0x07\r
+ #define B_TX_INT_HDCP_SYNC_DET_FAIL (1<<7)\r
+ #define B_TX_INT_VID_UNSTABLE (1<<6)\r
+ #define B_TX_INT_PKTACP (1<<5)\r
+ #define B_TX_INT_PKTNULL (1<<4)\r
+ #define B_TX_INT_PKTGENERAL (1<<3)\r
+ #define B_TX_INT_KSVLIST_CHK (1<<2)\r
+ #define B_TX_INT_AUTH_DONE (1<<1)\r
+ #define B_TX_INT_AUTH_FAIL (1<<0)\r
+\r
+#define REG_TX_INT_STAT3 0x08\r
+ #define B_TX_INT_AUD_CTS (1<<6)\r
+ #define B_TX_INT_VSYNC (1<<5)\r
+ #define B_TX_INT_VIDSTABLE (1<<4)\r
+ #define B_TX_INT_PKTMPG (1<<3)\r
+ #define B_TX_INT_PKTSPD (1<<2)\r
+ #define B_TX_INT_PKTAUD (1<<1)\r
+ #define B_TX_INT_PKTAVI (1<<0)\r
+\r
+#define REG_TX_INT_MASK1 0x09\r
+ #define B_TX_AUDIO_OVFLW_MASK (1<<7)\r
+ #define B_TX_DDC_NOACK_MASK (1<<5)\r
+ #define B_TX_DDC_FIFO_ERR_MASK (1<<4)\r
+ #define B_TX_DDC_BUS_HANG_MASK (1<<2)\r
+ #define B_TX_RXSEN_MASK (1<<1)\r
+ #define B_TX_HPD_MASK (1<<0)\r
+\r
+#define REG_TX_INT_MASK2 0x0A\r
+ #define B_TX_PKT_AVI_MASK (1<<7)\r
+ #define B_TX_PKT_VID_UNSTABLE_MASK (1<<6)\r
+ #define B_TX_PKT_ACP_MASK (1<<5)\r
+ #define B_TX_PKT_NULL_MASK (1<<4)\r
+ #define B_TX_PKT_GEN_MASK (1<<3)\r
+ #define B_TX_KSVLISTCHK_MASK (1<<2)\r
+ #define B_TX_AUTH_DONE_MASK (1<<1)\r
+ #define B_TX_AUTH_FAIL_MASK (1<<0)\r
+\r
+#define REG_TX_INT_MASK3 0x0B\r
+ #define B_TX_HDCP_SYNC_DET_FAIL_MASK (1<<6)\r
+ #define B_TX_AUDCTS_MASK (1<<5)\r
+ #define B_TX_VSYNC_MASK (1<<4)\r
+ #define B_TX_VIDSTABLE_MASK (1<<3)\r
+ #define B_TX_PKT_MPG_MASK (1<<2)\r
+ #define B_TX_PKT_SPD_MASK (1<<1)\r
+ #define B_TX_PKT_AUD_MASK (1<<0)\r
+\r
+#define REG_TX_INT_CLR0 0x0C\r
+ #define B_TX_CLR_PKTACP (1<<7)\r
+ #define B_TX_CLR_PKTNULL (1<<6)\r
+ #define B_TX_CLR_PKTGENERAL (1<<5)\r
+ #define B_TX_CLR_KSVLISTCHK (1<<4)\r
+ #define B_TX_CLR_AUTH_DONE (1<<3)\r
+ #define B_TX_CLR_AUTH_FAIL (1<<2)\r
+ #define B_TX_CLR_RXSENSE (1<<1)\r
+ #define B_TX_CLR_HPD (1<<0)\r
+\r
+#define REG_TX_INT_CLR1 0x0D\r
+ #define B_TX_CLR_VSYNC (1<<7)\r
+ #define B_TX_CLR_VIDSTABLE (1<<6)\r
+ #define B_TX_CLR_PKTMPG (1<<5)\r
+ #define B_TX_CLR_PKTSPD (1<<4)\r
+ #define B_TX_CLR_PKTAUD (1<<3)\r
+ #define B_TX_CLR_PKTAVI (1<<2)\r
+ #define B_TX_CLR_HDCP_SYNC_DET_FAIL (1<<1)\r
+ #define B_TX_CLR_VID_UNSTABLE (1<<0)\r
+\r
+#define REG_TX_SYS_STATUS 0x0E\r
+ // readonly\r
+ #define B_TX_INT_ACTIVE (1<<7)\r
+ #define B_TX_HPDETECT (1<<6)\r
+ #define B_TX_RXSENDETECT (1<<5)\r
+ #define B_TXVIDSTABLE (1<<4)\r
+ // read/write\r
+ #define O_TX_CTSINTSTEP 2\r
+ #define M_TX_CTSINTSTEP (3<<2)\r
+ #define B_TX_CLR_AUD_CTS (1<<1)\r
+ #define B_TX_INTACTDONE (1<<0)\r
+\r
+#define REG_TX_BANK_CTRL 0x0F\r
+ #define B_TX_BANK0 0\r
+ #define B_TX_BANK1 1\r
+\r
+// DDC\r
+\r
+#define REG_TX_DDC_MASTER_CTRL 0x10\r
+ #define B_TX_MASTERROM (1<<1)\r
+ #define B_TX_MASTERDDC (0<<1)\r
+ #define B_TX_MASTERHOST (1<<0)\r
+ #define B_TX_MASTERHDCP (0<<0)\r
+\r
+#define REG_TX_DDC_HEADER 0x11\r
+#define REG_TX_DDC_REQOFF 0x12\r
+#define REG_TX_DDC_REQCOUNT 0x13\r
+#define REG_TX_DDC_EDIDSEG 0x14\r
+#define REG_TX_DDC_CMD 0x15\r
+ #define CMD_DDC_SEQ_BURSTREAD 0\r
+ #define CMD_LINK_CHKREAD 2\r
+ #define CMD_EDID_READ 3\r
+ #define CMD_FIFO_CLR 9\r
+ #define CMD_GEN_SCLCLK 0xA\r
+ #define CMD_DDC_ABORT 0xF\r
+\r
+#define REG_TX_DDC_STATUS 0x16\r
+ #define B_TX_DDC_DONE (1<<7)\r
+ #define B_TX_DDC_ACT (1<<6)\r
+ #define B_TX_DDC_NOACK (1<<5)\r
+ #define B_TX_DDC_WAITBUS (1<<4)\r
+ #define B_TX_DDC_ARBILOSE (1<<3)\r
+ #define B_TX_DDC_ERROR (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE)\r
+ #define B_TX_DDC_FIFOFULL (1<<2)\r
+ #define B_TX_DDC_FIFOEMPTY (1<<1)\r
+\r
+#define REG_TX_DDC_READFIFO 0x17\r
+#define REG_TX_ROM_STARTADDR 0x18\r
+#define REG_TX_HDCP_HEADER 0x19\r
+#define REG_TX_ROM_HEADER 0x1A\r
+#define REG_TX_BUSHOLD_T 0x1B\r
+#define REG_TX_ROM_STAT 0x1C\r
+ #define B_TX_ROM_DONE (1<<7)\r
+ #define B_TX_ROM_ACTIVE (1<<6)\r
+ #define B_TX_ROM_NOACK (1<<5)\r
+ #define B_TX_ROM_WAITBUS (1<<4)\r
+ #define B_TX_ROM_ARBILOSE (1<<3)\r
+ #define B_TX_ROM_BUSHANG (1<<2)\r
+\r
+// HDCP\r
+#define REG_TX_AN_GENERATE 0x1F\r
+ #define B_TX_START_CIPHER_GEN 1\r
+ #define B_TX_STOP_CIPHER_GEN 0\r
+\r
+#define REG_TX_CLK_CTRL0 0x58\r
+ #define O_TX_OSCLK_SEL 5\r
+ #define M_TX_OSCLK_SEL 3\r
+ #define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4)\r
+ #define O_TX_EXT_MCLK_SEL 2\r
+ #define M_TX_EXT_MCLK_SEL (3<<O_TX_EXT_MCLK_SEL)\r
+ #define B_TX_EXT_128FS (0<<O_TX_EXT_MCLK_SEL)\r
+ #define B_TX_EXT_256FS (1<<O_TX_EXT_MCLK_SEL)\r
+ #define B_TX_EXT_512FS (2<<O_TX_EXT_MCLK_SEL)\r
+ #define B_TX_EXT_1024FS (3<<O_TX_EXT_MCLK_SEL)\r
+\r
+#define REG_TX_SHA_SEL 0x50\r
+#define REG_TX_SHA_RD_BYTE1 0x51\r
+#define REG_TX_SHA_RD_BYTE2 0x52\r
+#define REG_TX_SHA_RD_BYTE3 0x53\r
+#define REG_TX_SHA_RD_BYTE4 0x54\r
+#define REG_TX_AKSV_RD_BYTE5 0x55\r
+\r
+\r
+#define REG_TX_CLK_CTRL1 0x59\r
+ #define B_TX_EN_TXCLK_COUNT (1<<5)\r
+ #define B_TX_VDO_LATCH_EDGE (1<<3)\r
+\r
+#define REG_TX_CLK_STATUS1 0x5E\r
+#define REG_TX_CLK_STATUS2 0x5F\r
+ #define B_TX_IP_LOCK (1<<7)\r
+ #define B_TX_XP_LOCK (1<<6)\r
+ #define B_TX_OSF_LOCK (1<<5)\r
+\r
+#define REG_TX_AUD_COUNT 0x60\r
+#define REG_TX_AFE_DRV_CTRL 0x61\r
+\r
+ #define B_TX_AFE_DRV_PWD (1<<5)\r
+ #define B_TX_AFE_DRV_RST (1<<4)\r
+\r
+#define REG_TX_PLL_CTRL 0x6A\r
+\r
+// Input Data Format Register\r
+#define REG_TX_INPUT_MODE 0x70\r
+ #define O_TX_INCLKDLY 0\r
+ #define M_TX_INCLKDLY 3\r
+ #define B_TX_INDDR (1<<2)\r
+ #define B_TX_SYNCEMB (1<<3)\r
+ #define B_TX_2X656CLK (1<<4)\r
+ #define B_TX_PCLKDIV2 (1<<5)\r
+ #define M_TX_INCOLMOD (3<<6)\r
+ #define B_TX_IN_RGB 0\r
+ #define B_TX_IN_YUV422 (1<<6)\r
+ #define B_TX_IN_YUV444 (2<<6)\r
+\r
+#define REG_TX_TXFIFO_RST 0x71\r
+ #define B_TX_ENAVMUTERST 1\r
+ #define B_TXFFRST (1<<1)\r
+\r
+#define REG_TX_CSC_CTRL 0x72\r
+ #define B_HDMITX_CSC_BYPASS 0\r
+ #define B_HDMITX_CSC_RGB2YUV 2\r
+ #define B_HDMITX_CSC_YUV2RGB 3\r
+ #define M_TX_CSC_SEL 3\r
+ #define B_TX_EN_DITHER (1<<7)\r
+ #define B_TX_EN_UDFILTER (1<<6)\r
+ #define B_TX_DNFREE_GO (1<<5)\r
+\r
+#define SIZEOF_CSCMTX 21\r
+#define SIZEOF_CSCGAIN 6\r
+#define SIZEOF_CSCOFFSET 3\r
+\r
+\r
+#define REG_TX_CSC_YOFF 0x73\r
+#define REG_TX_CSC_COFF 0x74\r
+#define REG_TX_CSC_RGBOFF 0x75\r
+\r
+#define REG_TX_CSC_MTX11_L 0x76\r
+#define REG_TX_CSC_MTX11_H 0x77\r
+#define REG_TX_CSC_MTX12_L 0x78\r
+#define REG_TX_CSC_MTX12_H 0x79\r
+#define REG_TX_CSC_MTX13_L 0x7A\r
+#define REG_TX_CSC_MTX13_H 0x7B\r
+#define REG_TX_CSC_MTX21_L 0x7C\r
+#define REG_TX_CSC_MTX21_H 0x7D\r
+#define REG_TX_CSC_MTX22_L 0x7E\r
+#define REG_TX_CSC_MTX22_H 0x7F\r
+#define REG_TX_CSC_MTX23_L 0x80\r
+#define REG_TX_CSC_MTX23_H 0x81\r
+#define REG_TX_CSC_MTX31_L 0x82\r
+#define REG_TX_CSC_MTX31_H 0x83\r
+#define REG_TX_CSC_MTX32_L 0x84\r
+#define REG_TX_CSC_MTX32_H 0x85\r
+#define REG_TX_CSC_MTX33_L 0x86\r
+#define REG_TX_CSC_MTX33_H 0x87\r
+\r
+#define REG_TX_CSC_GAIN1V_L 0x88\r
+#define REG_TX_CSC_GAIN1V_H 0x89\r
+#define REG_TX_CSC_GAIN2V_L 0x8A\r
+#define REG_TX_CSC_GAIN2V_H 0x8B\r
+#define REG_TX_CSC_GAIN3V_L 0x8C\r
+#define REG_TX_CSC_GAIN3V_H 0x8D\r
+\r
+#define REG_TX_HVPol 0x90\r
+#define REG_TX_HfPixel 0x91\r
+#define REG_TX_HSSL 0x95\r
+#define REG_TX_HSEL 0x96\r
+#define REG_TX_HSH 0x97\r
+#define REG_TX_VSS1 0xA0\r
+#define REG_TX_VSE1 0xA1\r
+#define REG_TX_VSS2 0xA2\r
+#define REG_TX_VSE2 0xA3\r
+\r
+// HDMI General Control Registers\r
+\r
+#define REG_TX_HDMI_MODE 0xC0\r
+ #define B_TX_HDMI_MODE 1\r
+ #define B_TX_DVI_MODE 0\r
+#define REG_TX_AV_MUTE 0xC1\r
+#define REG_TX_GCP 0xC1\r
+ #define B_TX_CLR_AVMUTE 0\r
+ #define B_TX_SET_AVMUTE 1\r
+ #define B_TX_SETAVMUTE (1<<0)\r
+ #define B_TX_BLUE_SCR_MUTE (1<<1)\r
+ #define B_TX_NODEF_PHASE (1<<2)\r
+ #define B_TX_PHASE_RESYNC (1<<3)\r
+\r
+ #define O_TX_COLOR_DEPTH 4\r
+ #define M_TX_COLOR_DEPTH 7\r
+ #define B_TX_COLOR_DEPTH_MASK (M_TX_COLOR_DEPTH<<O_TX_COLOR_DEPTH)\r
+ #define B_TX_CD_NODEF 0\r
+ #define B_TX_CD_24 (4<<4)\r
+ #define B_TX_CD_30 (5<<4)\r
+ #define B_TX_CD_36 (6<<4)\r
+ #define B_TX_CD_48 (7<<4)\r
+#define REG_TX_PKT_GENERAL_CTRL 0xC6\r
+\r
+#define REG_TX_OESS_CYCLE 0xC3\r
+\r
+\r
+/////////////////////////////////////////////////////////////////////\r
+// Macro\r
+/////////////////////////////////////////////////////////////////////\r
+#define Switch_HDMITX_Bank(x) HDMITX_SetI2C_Byte(0x0f,1, (x)&1)\r
+#define HDMITX_OrReg_Byte(reg,ormask) HDMITX_SetI2C_Byte(reg,(ormask),(ormask))\r
+#define HDMITX_AndReg_Byte(reg,andmask) HDMITX_WriteI2C_Byte(reg,(HDMITX_ReadI2C_Byte(reg) & (andmask)))\r
+\r
+/////////////////////////////////////////////////////////////////////\r
+// data structure\r
+/////////////////////////////////////////////////////////////////////\r
+typedef struct _HDMITXDEV_STRUCT {\r
+\r
+ BYTE I2C_DEV ;\r
+ BYTE I2C_ADDR ;\r
+\r
+ /////////////////////////////////////////////////\r
+ // Interrupt Type\r
+ /////////////////////////////////////////////////\r
+ BYTE bIntType ; // = 0 ;\r
+ /////////////////////////////////////////////////\r
+ // Video Property\r
+ /////////////////////////////////////////////////\r
+ BYTE bInputVideoSignalType ; // for Sync Embedded,CCIR656,InputDDR\r
+ /////////////////////////////////////////////////\r
+ // Audio Property\r
+ /////////////////////////////////////////////////\r
+ BYTE bOutputAudioMode ; // = 0 ;\r
+ BYTE bAudioChannelSwap ; // = 0 ;\r
+ BYTE bAudioChannelEnable ;\r
+ BYTE bAudFs ;\r
+ unsigned long TMDSClock ;\r
+ unsigned long RCLK ;\r
+ BYTE bAuthenticated:1 ;\r
+ BYTE bHDMIMode: 1;\r
+ BYTE bIntPOL:1 ; // 0 = Low Active\r
+ BYTE bHPD:1 ;\r
+ // 2009/11/11 added by jj_tseng@ite.com.tw\r
+ BYTE bSPDIF_OUT;\r
+ BYTE TxEMEMStatus:1 ;\r
+ //~jau-chih.tseng@ite.com.tw 2009/11/11\r
+} HDMITXDEV ;\r
+\r
+\r
+\r
+//~jj_tseng@chipadvanced.com\r
+\r
+typedef struct structRegSetEntry {\r
+ BYTE offset ;\r
+ BYTE invAndMask ;\r
+ BYTE OrMask ;\r
+} RegSetEntry;\r
+\r
+#include "hdmitx_hdcp.h"\r
+#include "hdmitx_input.h"\r
+\r
+\r
+// Audio Channel Control\r
+#define REG_TX_AUDIO_CTRL0 0xE0\r
+ #define M_TX_AUD_SWL (3<<6)\r
+ #define M_TX_AUD_16BIT (0<<6)\r
+ #define M_TX_AUD_18BIT (1<<6)\r
+ #define M_TX_AUD_20BIT (2<<6)\r
+ #define M_TX_AUD_24BIT (3<<6)\r
+\r
+ #define B_TX_SPDIFTC (1<<5)\r
+\r
+ #define B_TX_AUD_SPDIF (1<<4)\r
+ #define B_TX_AUD_I2S (0<<4)\r
+ #define B_TX_AUD_EN_I2S3 (1<<3)\r
+ #define B_TX_AUD_EN_I2S2 (1<<2)\r
+ #define B_TX_AUD_EN_I2S1 (1<<1)\r
+ #define B_TX_AUD_EN_I2S0 (1<<0)\r
+ #define B_TX_AUD_EN_SPDIF 1\r
+\r
+#define REG_TX_AUDIO_CTRL1 0xE1\r
+ #define B_TX_AUD_FULLPKT (1<<6)\r
+\r
+ #define B_TX_AUDFMT_STD_I2S (0<<0)\r
+ #define B_TX_AUDFMT_32BIT_I2S (1<<0)\r
+ #define B_TX_AUDFMT_LEFT_JUSTIFY (0<<1)\r
+ #define B_TX_AUDFMT_RIGHT_JUSTIFY (1<<1)\r
+ #define B_TX_AUDFMT_DELAY_1T_TO_WS (0<<2)\r
+ #define B_TX_AUDFMT_NO_DELAY_TO_WS (1<<2)\r
+ #define B_TX_AUDFMT_WS0_LEFT (0<<3)\r
+ #define B_TX_AUDFMT_WS0_RIGHT (1<<3)\r
+ #define B_TX_AUDFMT_MSB_SHIFT_FIRST (0<<4)\r
+ #define B_TX_AUDFMT_LSB_SHIFT_FIRST (1<<4)\r
+ #define B_TX_AUDFMT_RISE_EDGE_SAMPLE_WS (0<<5)\r
+ #define B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS (1<<5)\r
+\r
+#define REG_TX_AUDIO_FIFOMAP 0xE2\r
+ #define O_TX_FIFO3SEL 6\r
+ #define O_TX_FIFO2SEL 4\r
+ #define O_TX_FIFO1SEL 2\r
+ #define O_TX_FIFO0SEL 0\r
+ #define B_TX_SELSRC3 3\r
+ #define B_TX_SELSRC2 2\r
+ #define B_TX_SELSRC1 1\r
+ #define B_TX_SELSRC0 0\r
+\r
+#define REG_TX_AUDIO_CTRL3 0xE3\r
+ #define B_TX_AUD_MULCH (1<<7)\r
+ #define B_TX_EN_ZERO_CTS (1<<6)\r
+ #define B_TX_CHSTSEL (1<<4)\r
+ #define B_TX_S3RLCHG (1<<3)\r
+ #define B_TX_S2RLCHG (1<<2)\r
+ #define B_TX_S1RLCHG (1<<1)\r
+ #define B_TX_S0RLCHG (1<<0)\r
+\r
+#define REG_TX_AUD_SRCVALID_FLAT 0xE4\r
+ #define B_TX_AUD_SPXFLAT_SRC3 (1<<7)\r
+ #define B_TX_AUD_SPXFLAT_SRC2 (1<<6)\r
+ #define B_TX_AUD_SPXFLAT_SRC1 (1<<5)\r
+ #define B_TX_AUD_SPXFLAT_SRC0 (1<<4)\r
+ #define B_TX_AUD_ERR2FLAT (1<<3)\r
+ #define B_TX_AUD_S3VALID (1<<2)\r
+ #define B_TX_AUD_S2VALID (1<<1)\r
+ #define B_TX_AUD_S1VALID (1<<0)\r
+\r
+#define REG_TX_AUD_HDAUDIO 0xE5\r
+#define B_TX_HBR (1<<3)\r
+#define B_TX_DSD (1<<1)\r
+\r
+//////////////////////////////////////////\r
+// Bank 1\r
+//////////////////////////////////////////\r
+\r
+#define REGPktAudCTS0 0x30 // 7:0\r
+#define REGPktAudCTS1 0x31 // 15:8\r
+#define REGPktAudCTS2 0x32 // 19:16\r
+#define REGPktAudN0 0x33 // 7:0\r
+#define REGPktAudN1 0x34 // 15:8\r
+#define REGPktAudN2 0x35 // 19:16\r
+#define REGPktAudCTSCnt0 0x35 // 3:0\r
+#define REGPktAudCTSCnt1 0x36 // 11:4\r
+#define REGPktAudCTSCnt2 0x37 // 19:12\r
+\r
+\r
+#define REG_TX_AUDCHST_MODE 0x91 // 191 REG_TX_AUD_CHSTD[2:0] 6:4\r
+ // REG_TX_AUD_CHSTC 3\r
+ // REG_TX_AUD_NLPCM 2\r
+ // REG_TX_AUD_MONO 0\r
+#define REG_TX_AUDCHST_CAT 0x92 // 192 REG_TX_AUD_CHSTCAT 7:0\r
+#define REG_TX_AUDCHST_SRCNUM 0x93 // 193 REG_TX_AUD_CHSTSRC 3:0\r
+#define REG_TX_AUD0CHST_CHTNUM 0x94 // 194 REG_TX_AUD0_CHSTCHR 7:4\r
+ // REG_TX_AUD0_CHSTCHL 3:0\r
+#define REG_TX_AUD1CHST_CHTNUM 0x95 // 195 REG_TX_AUD1_CHSTCHR 7:4\r
+ // REG_TX_AUD1_CHSTCHL 3:0\r
+#define REG_TX_AUD2CHST_CHTNUM 0x96 // 196 REG_TX_AUD2_CHSTCHR 7:4\r
+ // REG_TX_AUD2_CHSTCHL 3:0\r
+#define REG_TX_AUD3CHST_CHTNUM 0x97 // 197 REG_TX_AUD3_CHSTCHR 7:4\r
+ // REG_TX_AUD3_CHSTCHL 3:0\r
+#define REG_TX_AUDCHST_CA_FS 0x98 // 198 REG_TX_AUD_CHSTCA 5:4\r
+ // REG_TX_AUD_CHSTFS 3:0\r
+#define REG_TX_AUDCHST_OFS_WL 0x99 // 199 REG_TX_AUD_CHSTOFS 7:4\r
+ // REG_TX_AUD_CHSTWL 3:0\r
+\r
+#define REG_TX_PKT_SINGLE_CTRL 0xC5\r
+ #define B_TX_SINGLE_PKT 1\r
+ #define B_TX_BURST_PKT\r
+ #define B_TX_SW_CTS (1<<1)\r
+\r
+#define REG_TX_NULL_CTRL 0xC9\r
+#define REG_TX_ACP_CTRL 0xCA\r
+#define REG_TX_ISRC1_CTRL 0xCB\r
+#define REG_TX_ISRC2_CTRL 0xCC\r
+#define REG_TX_AVI_INFOFRM_CTRL 0xCD\r
+#define REG_TX_AUD_INFOFRM_CTRL 0xCE\r
+#define REG_TX_SPD_INFOFRM_CTRL 0xCF\r
+#define REG_TX_MPG_INFOFRM_CTRL 0xD0\r
+ #define B_TX_ENABLE_PKT 1\r
+ #define B_TX_REPEAT_PKT (1<<1)\r
+\r
+#define REG_TX_3D_INFO_CTRL 0xD2\r
+\r
+//////////////////////////////////////////\r
+// COMMON PACKET for NULL,ISRC1,ISRC2,SPD\r
+//////////////////////////////////////////\r
+\r
+#define REG_TX_PKT_HB00 0x38\r
+#define REG_TX_PKT_HB01 0x39\r
+#define REG_TX_PKT_HB02 0x3A\r
+\r
+#define REG_TX_PKT_PB00 0x3B\r
+#define REG_TX_PKT_PB01 0x3C\r
+#define REG_TX_PKT_PB02 0x3D\r
+#define REG_TX_PKT_PB03 0x3E\r
+#define REG_TX_PKT_PB04 0x3F\r
+#define REG_TX_PKT_PB05 0x40\r
+#define REG_TX_PKT_PB06 0x41\r
+#define REG_TX_PKT_PB07 0x42\r
+#define REG_TX_PKT_PB08 0x43\r
+#define REG_TX_PKT_PB09 0x44\r
+#define REG_TX_PKT_PB10 0x45\r
+#define REG_TX_PKT_PB11 0x46\r
+#define REG_TX_PKT_PB12 0x47\r
+#define REG_TX_PKT_PB13 0x48\r
+#define REG_TX_PKT_PB14 0x49\r
+#define REG_TX_PKT_PB15 0x4A\r
+#define REG_TX_PKT_PB16 0x4B\r
+#define REG_TX_PKT_PB17 0x4C\r
+#define REG_TX_PKT_PB18 0x4D\r
+#define REG_TX_PKT_PB19 0x4E\r
+#define REG_TX_PKT_PB20 0x4F\r
+#define REG_TX_PKT_PB21 0x50\r
+#define REG_TX_PKT_PB22 0x51\r
+#define REG_TX_PKT_PB23 0x52\r
+#define REG_TX_PKT_PB24 0x53\r
+#define REG_TX_PKT_PB25 0x54\r
+#define REG_TX_PKT_PB26 0x55\r
+#define REG_TX_PKT_PB27 0x56\r
+\r
+#define REG_TX_AVIINFO_DB1 0x58\r
+#define REG_TX_AVIINFO_DB2 0x59\r
+#define REG_TX_AVIINFO_DB3 0x5A\r
+#define REG_TX_AVIINFO_DB4 0x5B\r
+#define REG_TX_AVIINFO_DB5 0x5C\r
+#define REG_TX_AVIINFO_DB6 0x5E\r
+#define REG_TX_AVIINFO_DB7 0x5F\r
+#define REG_TX_AVIINFO_DB8 0x60\r
+#define REG_TX_AVIINFO_DB9 0x61\r
+#define REG_TX_AVIINFO_DB10 0x62\r
+#define REG_TX_AVIINFO_DB11 0x63\r
+#define REG_TX_AVIINFO_DB12 0x64\r
+#define REG_TX_AVIINFO_DB13 0x65\r
+#define REG_TX_AVIINFO_SUM 0x5D\r
+\r
+#define REG_TX_PKT_AUDINFO_CC 0x68 // [2:0]\r
+#define REG_TX_PKT_AUDINFO_SF 0x69 // [4:2]\r
+#define REG_TX_PKT_AUDINFO_CA 0x6B // [7:0]\r
+\r
+#define REG_TX_PKT_AUDINFO_DM_LSV 0x6C // [7][6:3]\r
+#define REG_TX_PKT_AUDINFO_SUM 0x6D // [7:0]\r
+\r
+// Source Product Description Info Frame\r
+#define REG_TX_PKT_SPDINFO_SUM 0x70\r
+#define REG_TX_PKT_SPDINFO_PB1 0x71\r
+#define REG_TX_PKT_SPDINFO_PB2 0x72\r
+#define REG_TX_PKT_SPDINFO_PB3 0x73\r
+#define REG_TX_PKT_SPDINFO_PB4 0x74\r
+#define REG_TX_PKT_SPDINFO_PB5 0x75\r
+#define REG_TX_PKT_SPDINFO_PB6 0x76\r
+#define REG_TX_PKT_SPDINFO_PB7 0x77\r
+#define REG_TX_PKT_SPDINFO_PB8 0x78\r
+#define REG_TX_PKT_SPDINFO_PB9 0x79\r
+#define REG_TX_PKT_SPDINFO_PB10 0x7A\r
+#define REG_TX_PKT_SPDINFO_PB11 0x7B\r
+#define REG_TX_PKT_SPDINFO_PB12 0x7C\r
+#define REG_TX_PKT_SPDINFO_PB13 0x7D\r
+#define REG_TX_PKT_SPDINFO_PB14 0x7E\r
+#define REG_TX_PKT_SPDINFO_PB15 0x7F\r
+#define REG_TX_PKT_SPDINFO_PB16 0x80\r
+#define REG_TX_PKT_SPDINFO_PB17 0x81\r
+#define REG_TX_PKT_SPDINFO_PB18 0x82\r
+#define REG_TX_PKT_SPDINFO_PB19 0x83\r
+#define REG_TX_PKT_SPDINFO_PB20 0x84\r
+#define REG_TX_PKT_SPDINFO_PB21 0x85\r
+#define REG_TX_PKT_SPDINFO_PB22 0x86\r
+#define REG_TX_PKT_SPDINFO_PB23 0x87\r
+#define REG_TX_PKT_SPDINFO_PB24 0x88\r
+#define REG_TX_PKT_SPDINFO_PB25 0x89\r
+\r
+#define REG_TX_PKT_MPGINFO_FMT 0x8A\r
+#define B_TX_MPG_FR 1\r
+#define B_TX_MPG_MF_I (1<<1)\r
+#define B_TX_MPG_MF_B (2<<1)\r
+#define B_TX_MPG_MF_P (3<<1)\r
+#define B_TX_MPG_MF_MASK (3<<1)\r
+#define REG_TX_PKG_MPGINFO_DB0 0x8B\r
+#define REG_TX_PKG_MPGINFO_DB1 0x8C\r
+#define REG_TX_PKG_MPGINFO_DB2 0x8D\r
+#define REG_TX_PKG_MPGINFO_DB3 0x8E\r
+#define REG_TX_PKG_MPGINFO_SUM 0x8F\r
+\r
+#define Frame_Pcaking 0\r
+#define Top_and_Botton 6\r
+#define Side_by_Side 8\r
+\r
+////////////////////////////////////////////////////\r
+// Function Prototype\r
+////////////////////////////////////////////////////\r
+#define hdmitx_ENABLE_NULL_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_ACP_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ACP_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_ISRC1_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC1_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_ISRC2_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC2_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_AVI_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AVI_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_AUD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AUD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_SPD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_SPD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_MPG_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_ENABLE_GeneralPurpose_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }\r
+#define hdmitx_DISABLE_VSDB_PKT() { HDMITX_WriteI2C_Byte(REG_TX_3D_INFO_CTRL,0); }\r
+#define hdmitx_DISABLE_NULL_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,0); }\r
+#define hdmitx_DISABLE_ACP_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ACP_CTRL,0); }\r
+#define hdmitx_DISABLE_ISRC1_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC1_CTRL,0); }\r
+#define hdmitx_DISABLE_ISRC2_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC2_CTRL,0); }\r
+#define hdmitx_DISABLE_AVI_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AVI_INFOFRM_CTRL,0); }\r
+#define hdmitx_DISABLE_AUD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AUD_INFOFRM_CTRL,0); }\r
+#define hdmitx_DISABLE_SPD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_SPD_INFOFRM_CTRL,0); }\r
+#define hdmitx_DISABLE_MPG_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,0); }\r
+#define hdmitx_DISABLE_GeneralPurpose_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,0); }\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// External Interface\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+typedef enum {\r
+ PCLK_LOW = 0 ,\r
+ PCLK_MEDIUM,\r
+ PCLK_HIGH\r
+} VIDEOPCLKLEVEL ;\r
+\r
+// 2008/08/18 added by jj_tseng@chipadvanced.com\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+void InitHDMITX();\r
+void HDMITX_InitTxDev(HDMITXDEV *pInstance);\r
+BYTE CheckHDMITX(BYTE *pHPD,BYTE *pHPDChange);\r
+BOOL getHDMITX_LinkStatus();\r
+void HDMITX_PowerOn();\r
+void HDMITX_PowerDown();\r
+\r
+void hdmitx_LoadRegSetting(RegSetEntry table[]);\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX video function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+void HDMITX_DisableVideoOutput();\r
+BOOL HDMITX_EnableVideoOutput(VIDEOPCLKLEVEL level,BYTE inputColorMode,BYTE outputColorMode,BYTE bHDMI);\r
+BOOL setHDMITX_VideoSignalType(BYTE inputSignalType);\r
+void setHDMITX_ColorDepthPhase(BYTE ColorDepth,BYTE bPhase);\r
+\r
+// TBD ...\r
+// #ifdef SUPPORT_DEGEN\r
+// BOOL ProgramDEGenModeByID(MODE_ID id,BYTE bInputSignalType);\r
+// #endif // SUPPORT_DEGEN\r
+\r
+#ifdef SUPPORT_SYNCEMBEDDED\r
+ BOOL setHDMITX_SyncEmbeddedByVIC(BYTE VIC,BYTE bInputSignalType);\r
+#endif\r
+\r
+\r
+void hdmitx_SetInputMode(BYTE InputMode,BYTE bInputSignalType);\r
+void hdmitx_SetCSCScale(BYTE bInputMode,BYTE bOutputMode);\r
+void hdmitx_SetupAFE(VIDEOPCLKLEVEL level);\r
+void hdmitx_FireAFE();\r
+\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX audio function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+void HDMITX_DisableAudioOutput();\r
+void HDMITX_EnableAudioOutput(BYTE AudioType, BOOL bSPDIF, ULONG SampleFreq, BYTE ChNum, BYTE *pIEC60958ChStat, ULONG TMDSClock);\r
+\r
+void setHDMITX_AudioChannelEnable(BOOL EnableAudio_b);\r
+void setHDMITX_ChStat(BYTE ucIEC60958ChStat[]);\r
+void setHDMITX_DSDAudio();\r
+void setHDMITX_HBRAudio(BOOL bSPDIF);\r
+void setHDMITX_LPCMAudio(BYTE AudioSrcNum, BYTE AudSWL, BOOL bSPDIF);\r
+void setHDMITX_NCTS(BYTE Fs);\r
+void setHDMITX_NLPCMAudio(BOOL bSPDIF);\r
+void setHDMITX_UpdateChStatFs(ULONG Fs);\r
+\r
+BOOL hdmitx_IsAudioChang();\r
+void hdmitx_AutoAdjustAudio();\r
+\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX hdcp function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+BOOL HDMITX_EnableHDCP(BYTE bEnable);\r
+BOOL getHDMITX_AuthenticationDone();\r
+\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX pkt/infoframe function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+void setHDMITX_AVMute(BYTE bEnable);\r
+BOOL HDMITX_EnableAVIInfoFrame(BYTE bEnable,BYTE *pAVIInfoFrame);\r
+BOOL HDMITX_EnableAudioInfoFrame(BYTE bEnable,BYTE *pAudioInfoFrame);\r
+BOOL HDMITX_EnableVSInfoFrame(BYTE bEnable,BYTE *pVSInfoFrame);\r
+\r
+SYS_STATUS hdmitx_SetAVIInfoFrame(AVI_InfoFrame *pAVIInfoFrame);\r
+SYS_STATUS hdmitx_SetAudioInfoFrame(Audio_InfoFrame *pAudioInfoFrame);\r
+SYS_STATUS hdmitx_SetSPDInfoFrame(SPD_InfoFrame *pSPDInfoFrame);\r
+SYS_STATUS hdmitx_SetMPEGInfoFrame(MPEG_InfoFrame *pMPGInfoFrame);\r
+SYS_STATUS hdmitx_SetVSIInfoFrame(VendorSpecific_InfoFrame *pVSIInfoFrame);\r
+SYS_STATUS hdmitx_Set_GeneralPurpose_PKT(BYTE *pData);\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+// HDMITX ddc/edid function prototype\r
+/////////////////////////////////////////////////////////////////////////////////////\r
+BOOL getHDMITX_EDIDBlock(int EDIDBlockID,BYTE *pEDIDData);\r
+SYS_STATUS getHDMITX_EDIDBytes(BYTE *pData,BYTE bSegment,BYTE offset,SHORT Count);\r
+\r
+void hdmitx_GenerateDDCSCLK();\r
+void hdmitx_ClearDDCFIFO();\r
+void hdmitx_AbortDDC();\r
+\r
+#if defined(Debug_message) && (Debug_message==1)\r
+ void DumpHDMITXReg();\r
+#else\r
+ #define DumpHDMITXReg()\r
+#endif\r
+\r
+#define delay1ms(x) mdelay(x)\r
+////////////////////////////////////////////////////////////////////\r
+// Required Interfance\r
+////////////////////////////////////////////////////////////////////\r
+BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);\r
+SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);\r
+SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);\r
+SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);\r
+SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);\r
+//SYS_STATUS HDMITX_ToggleBit(BYTE Reg,BYTE n);\r
+\r
+\r
+#endif // _HDMITX_DRV_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_hdcp.c>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#include "hdmitx.h"\r
+#include "hdmitx_drv.h"\r
+\r
+static BYTE countbit(BYTE b);\r
+\r
+extern HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT] ;\r
+\r
+#ifdef SUPPORT_SHA\r
+_XDATA BYTE SHABuff[64] ;\r
+_XDATA BYTE V[20] ;\r
+_XDATA BYTE KSVList[32] ;\r
+_XDATA BYTE Vr[20] ;\r
+_XDATA BYTE M0[8] ;\r
+#endif\r
+\r
+BOOL HDMITX_EnableHDCP(BYTE bEnable)\r
+{\r
+#ifdef SUPPORT_HDCP\r
+ if(bEnable)\r
+ {\r
+ if(ER_FAIL == hdmitx_hdcp_Authenticate())\r
+ {\r
+ //printf("ER_FAIL == hdmitx_hdcp_Authenticate\n");\r
+ hdmitx_hdcp_ResetAuth();\r
+ return FALSE ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hdmiTxDev[0].bAuthenticated=FALSE;\r
+ hdmitx_hdcp_ResetAuth();\r
+ }\r
+#endif\r
+ return TRUE ;\r
+}\r
+\r
+#ifdef SUPPORT_HDCP\r
+\r
+BOOL getHDMITX_AuthenticationDone()\r
+{\r
+ //HDCP_DEBUG_PRINTF((" getHDMITX_AuthenticationDone() = %s\n",hdmiTxDev[0].bAuthenticated?"TRUE":"FALSE" ));\r
+ return hdmiTxDev[0].bAuthenticated;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Authentication\r
+//////////////////////////////////////////////////////////////////////\r
+void hdmitx_hdcp_ClearAuthInterrupt()\r
+{\r
+ // BYTE uc ;\r
+ // uc = HDMITX_ReadI2C_Byte(REG_TX_INT_MASK2) & (~(B_TX_KSVLISTCHK_MASK|B_TX_AUTH_DONE_MASK|B_TX_AUTH_FAIL_MASK));\r
+ HDMITX_SetI2C_Byte(REG_TX_INT_MASK2, B_TX_KSVLISTCHK_MASK|B_TX_AUTH_DONE_MASK|B_TX_AUTH_FAIL_MASK, 0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR0,B_TX_CLR_AUTH_FAIL|B_TX_CLR_AUTH_DONE|B_TX_CLR_KSVLISTCHK);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR1,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,B_TX_INTACTDONE);\r
+}\r
+\r
+void hdmitx_hdcp_ResetAuth()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_LISTCTRL,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDCP_DESIRE,0);\r
+ HDMITX_OrReg_Byte(REG_TX_SW_RST,B_TX_HDCP_RST_HDMITX);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ hdmitx_hdcp_ClearAuthInterrupt();\r
+ hdmitx_AbortDDC();\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_Auth_Fire()\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: write anything to reg21 to enable HDCP authentication by HW\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_Auth_Fire()\r
+{\r
+ // HDCP_DEBUG_PRINTF(("hdmitx_hdcp_Auth_Fire():\n"));\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHDCP); // MASTERHDCP,no need command but fire.\r
+ HDMITX_WriteI2C_Byte(REG_TX_AUTHFIRE,1);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_StartAnCipher\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: Start the Cipher to free run for random number. When stop,An is\r
+// ready in Reg30.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_StartAnCipher()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_AN_GENERATE,B_TX_START_CIPHER_GEN);\r
+ delay1ms(1); // delay 1 ms\r
+}\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_StopAnCipher\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: Stop the Cipher,and An is ready in Reg30.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_StopAnCipher()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_AN_GENERATE,B_TX_STOP_CIPHER_GEN);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_GenerateAn\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: start An ciper random run at first,then stop it. Software can get\r
+// an in reg30~reg38,the write to reg28~2F\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_GenerateAn()\r
+{\r
+ BYTE Data[8];\r
+ BYTE i=0;\r
+#if 1\r
+ hdmitx_hdcp_StartAnCipher();\r
+ // HDMITX_WriteI2C_Byte(REG_TX_AN_GENERATE,B_TX_START_CIPHER_GEN);\r
+ // delay1ms(1); // delay 1 ms\r
+ // HDMITX_WriteI2C_Byte(REG_TX_AN_GENERATE,B_TX_STOP_CIPHER_GEN);\r
+\r
+ hdmitx_hdcp_StopAnCipher();\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ // new An is ready in reg30\r
+ HDMITX_ReadI2C_ByteN(REG_TX_AN_GEN,Data,8);\r
+#else\r
+ Data[0] = 0 ;Data[1] = 0 ;Data[2] = 0 ;Data[3] = 0 ;\r
+ Data[4] = 0 ;Data[5] = 0 ;Data[6] = 0 ;Data[7] = 0 ;\r
+#endif\r
+ for(i=0;i<8;i++)\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_AN+i,Data[i]);\r
+ }\r
+ //HDMITX_WriteI2C_ByteN(REG_TX_AN,Data,8);\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_GetBCaps\r
+// Parameter: pBCaps - pointer of byte to get BCaps.\r
+// pBStatus - pointer of two bytes to get BStatus\r
+// Return: ER_SUCCESS if successfully got BCaps and BStatus.\r
+// Remark: get B status and capability from HDCP reciever via DDC bus.\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_hdcp_GetBCaps(PBYTE pBCaps ,PUSHORT pBStatus)\r
+{\r
+ BYTE ucdata ;\r
+ BYTE TimeOut ;\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_HEADER,DDC_HDCP_ADDRESS);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQOFF,0x40); // BCaps offset\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQCOUNT,3);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);\r
+\r
+ for(TimeOut = 200 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ delay1ms(1);\r
+\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+\r
+ if(ucdata & B_TX_DDC_DONE)\r
+ {\r
+ //HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps(): DDC Done.\n"));\r
+ break ;\r
+ }\r
+ if(ucdata & B_TX_DDC_ERROR)\r
+ {\r
+// HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps(): DDC fail by reg16=%02X.\n",ucdata));\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+#if 1\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_BSTAT+1);\r
+\r
+ *pBStatus = (USHORT)ucdata ;\r
+ *pBStatus <<= 8 ;\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_BSTAT);\r
+ *pBStatus |= ((USHORT)ucdata&0xFF);\r
+ *pBCaps = HDMITX_ReadI2C_Byte(REG_TX_BCAP);\r
+#else\r
+ *pBCaps = HDMITX_ReadI2C_Byte(0x17);\r
+ *pBStatus = HDMITX_ReadI2C_Byte(0x17) & 0xFF ;\r
+ *pBStatus |= (int)(HDMITX_ReadI2C_Byte(0x17)&0xFF)<<8;\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps(): ucdata = %02X\n",(int)HDMITX_ReadI2C_Byte(0x16)));\r
+#endif\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_GetBKSV\r
+// Parameter: pBKSV - pointer of 5 bytes buffer for getting BKSV\r
+// Return: ER_SUCCESS if successfuly got BKSV from Rx.\r
+// Remark: Get BKSV from HDCP reciever.\r
+// Side-Effect: N/A\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_hdcp_GetBKSV(BYTE *pBKSV)\r
+{\r
+ BYTE ucdata ;\r
+ BYTE TimeOut ;\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_HEADER,DDC_HDCP_ADDRESS);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQOFF,0x00); // BKSV offset\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQCOUNT,5);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);\r
+\r
+ for(TimeOut = 200 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ delay1ms(1);\r
+\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+ if(ucdata & B_TX_DDC_DONE)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps(): DDC Done.\n"));\r
+ break ;\r
+ }\r
+ if(ucdata & B_TX_DDC_ERROR)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps(): DDC No ack or arbilose,%x,maybe cable did not connected. Fail.\n",ucdata));\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ HDMITX_ReadI2C_ByteN(REG_TX_BKSV,(PBYTE)pBKSV,5);\r
+\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function:hdmitx_hdcp_Authenticate\r
+// Parameter: N/A\r
+// Return: ER_SUCCESS if Authenticated without error.\r
+// Remark: do Authentication with Rx\r
+// Side-Effect:\r
+// 1. hdmiTxDev[0].bAuthenticated global variable will be TRUE when authenticated.\r
+// 2. Auth_done interrupt and AUTH_FAIL interrupt will be enabled.\r
+//////////////////////////////////////////////////////////////////////\r
+static BYTE countbit(BYTE b)\r
+{\r
+ BYTE i,count ;\r
+ for( i = 0, count = 0 ; i < 8 ; i++ )\r
+ {\r
+ if( b & (1<<i) )\r
+ {\r
+ count++ ;\r
+ }\r
+ }\r
+ return count ;\r
+}\r
+\r
+void hdmitx_hdcp_Reset()\r
+{\r
+ BYTE uc ;\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_SW_RST) | B_TX_HDCP_RST_HDMITX ;\r
+ HDMITX_WriteI2C_Byte(REG_TX_SW_RST,uc);\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDCP_DESIRE,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_LISTCTRL,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHOST);\r
+ hdmitx_ClearDDCFIFO();\r
+ hdmitx_AbortDDC();\r
+}\r
+\r
+SYS_STATUS hdmitx_hdcp_Authenticate()\r
+{\r
+ BYTE ucdata ;\r
+ BYTE BCaps ;\r
+ USHORT BStatus ;\r
+ USHORT TimeOut ;\r
+\r
+ BYTE revoked = FALSE ;\r
+ BYTE BKSV[5] ;\r
+\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+ if(0==(B_TXVIDSTABLE&HDMITX_ReadI2C_Byte(REG_TX_SYS_STATUS)))\r
+ {\r
+ return ER_FAIL;\r
+ }\r
+ // Authenticate should be called after AFE setup up.\r
+\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_Authenticate():\n"));\r
+ hdmitx_hdcp_Reset();\r
+\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ for( TimeOut = 0 ; TimeOut < 80 ; TimeOut++ )\r
+ {\r
+ delay1ms(15);\r
+\r
+ if(hdmitx_hdcp_GetBCaps(&BCaps,&BStatus) != ER_SUCCESS)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetBCaps fail.\n"));\r
+ return ER_FAIL ;\r
+ }\r
+ // HDCP_DEBUG_PRINTF(("(%d)Reg16 = %02X\n",idx++,(int)HDMITX_ReadI2C_Byte(0x16)));\r
+\r
+ if(B_TX_HDMI_MODE == (HDMITX_ReadI2C_Byte(REG_TX_HDMI_MODE) & B_TX_HDMI_MODE ))\r
+ {\r
+ if((BStatus & B_TX_CAP_HDMI_MODE)==B_TX_CAP_HDMI_MODE)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((BStatus & B_TX_CAP_HDMI_MODE)!=B_TX_CAP_HDMI_MODE)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ /*\r
+ if((BStatus & M_TX_DOWNSTREAM_COUNT)> 6)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("Down Stream Count %d is over maximum supported number 6,fail.\n",(int)(BStatus & M_TX_DOWNSTREAM_COUNT)));\r
+ return ER_FAIL ;\r
+ }\r
+ */\r
+ HDCP_DEBUG_PRINTF(("BCAPS = %02X BSTATUS = %04X\n", (int)BCaps, BStatus));\r
+ hdmitx_hdcp_GetBKSV(BKSV);\r
+ HDCP_DEBUG_PRINTF(("BKSV %02X %02X %02X %02X %02X\n",(int)BKSV[0],(int)BKSV[1],(int)BKSV[2],(int)BKSV[3],(int)BKSV[4]));\r
+\r
+ for(TimeOut = 0, ucdata = 0 ; TimeOut < 5 ; TimeOut ++)\r
+ {\r
+ ucdata += countbit(BKSV[TimeOut]);\r
+ }\r
+ if( ucdata != 20 )\r
+ {\r
+ HDCP_DEBUG_PRINTF(("countbit error\n"));\r
+ return ER_FAIL ;\r
+\r
+ }\r
+ Switch_HDMITX_Bank(0); // switch bank action should start on direct register writting of each function.\r
+\r
+ HDMITX_AndReg_Byte(REG_TX_SW_RST,~(B_TX_HDCP_RST_HDMITX));\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_HDCP_DESIRE,B_TX_CPDESIRE);\r
+ hdmitx_hdcp_ClearAuthInterrupt();\r
+\r
+ hdmitx_hdcp_GenerateAn();\r
+ HDMITX_WriteI2C_Byte(REG_TX_LISTCTRL,0);\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+\r
+ hdmitx_ClearDDCFIFO();\r
+\r
+ if((BCaps & B_TX_CAP_HDMI_REPEATER) == 0)\r
+ {\r
+ hdmitx_hdcp_Auth_Fire();\r
+ // wait for status ;\r
+\r
+ for(TimeOut = 250 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ delay1ms(5); // delay 1ms\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_AUTH_STAT);\r
+ // HDCP_DEBUG_PRINTF(("reg46 = %02x reg16 = %02x\n",(int)ucdata,(int)HDMITX_ReadI2C_Byte(0x16)));\r
+\r
+ if(ucdata & B_TX_AUTH_DONE)\r
+ {\r
+ hdmiTxDev[0].bAuthenticated = TRUE ;\r
+ break ;\r
+ }\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT2);\r
+ if(ucdata & B_TX_INT_AUTH_FAIL)\r
+ {\r
+\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR0,B_TX_CLR_AUTH_FAIL);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR1,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,B_TX_INTACTDONE);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,0);\r
+\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_Authenticate()-receiver: Authenticate fail\n"));\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_Authenticate()-receiver: Time out. return fail\n"));\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+ return ER_FAIL ;\r
+ }\r
+ return ER_SUCCESS ;\r
+ }\r
+ return hdmitx_hdcp_Authenticate_Repeater();\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_VerifyIntegration\r
+// Parameter: N/A\r
+// Return: ER_SUCCESS if success,if AUTH_FAIL interrupt status,return fail.\r
+// Remark: no used now.\r
+// Side-Effect:\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+SYS_STATUS hdmitx_hdcp_VerifyIntegration()\r
+{\r
+ // if any interrupt issued a Auth fail,returned the Verify Integration fail.\r
+\r
+ if(HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1) & B_TX_INT_AUTH_FAIL)\r
+ {\r
+ hdmitx_hdcp_ClearAuthInterrupt();\r
+ hdmiTxDev[0].bAuthenticated = FALSE ;\r
+ return ER_FAIL ;\r
+ }\r
+ if(hdmiTxDev[0].bAuthenticated == TRUE)\r
+ {\r
+ return ER_SUCCESS ;\r
+ }\r
+ return ER_FAIL ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_Authenticate_Repeater\r
+// Parameter: BCaps and BStatus\r
+// Return: ER_SUCCESS if success,if AUTH_FAIL interrupt status,return fail.\r
+// Remark:\r
+// Side-Effect: as Authentication\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_CancelRepeaterAuthenticate()\r
+{\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_CancelRepeaterAuthenticate"));\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);\r
+ hdmitx_AbortDDC();\r
+ HDMITX_WriteI2C_Byte(REG_TX_LISTCTRL,B_TX_LISTFAIL|B_TX_LISTDONE);\r
+ hdmitx_hdcp_ClearAuthInterrupt();\r
+}\r
+\r
+void hdmitx_hdcp_ResumeRepeaterAuthenticate()\r
+{\r
+ HDMITX_WriteI2C_Byte(REG_TX_LISTCTRL,B_TX_LISTDONE);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHDCP);\r
+}\r
+\r
+#if 0 // def SUPPORT_SHA\r
+// #define SHA_BUFF_COUNT 17\r
+// _XDATA ULONG w[SHA_BUFF_COUNT];\r
+//\r
+// _XDATA ULONG sha[5] ;\r
+//\r
+// #define rol(x,y) (((x) << (y)) | (((ULONG)x) >> (32-y)))\r
+//\r
+// void SHATransform(ULONG * h)\r
+// {\r
+// int t,i;\r
+// ULONG tmp ;\r
+//\r
+// h[0] = 0x67452301 ;\r
+// h[1] = 0xefcdab89;\r
+// h[2] = 0x98badcfe;\r
+// h[3] = 0x10325476;\r
+// h[4] = 0xc3d2e1f0;\r
+// for( t = 0 ; t < 80 ; t++ )\r
+// {\r
+// if((t>=16)&&(t<80)) {\r
+// i=(t+SHA_BUFF_COUNT-3)%SHA_BUFF_COUNT;\r
+// tmp = w[i];\r
+// i=(t+SHA_BUFF_COUNT-8)%SHA_BUFF_COUNT;\r
+// tmp ^= w[i];\r
+// i=(t+SHA_BUFF_COUNT-14)%SHA_BUFF_COUNT;\r
+// tmp ^= w[i];\r
+// i=(t+SHA_BUFF_COUNT-16)%SHA_BUFF_COUNT;\r
+// tmp ^= w[i];\r
+// w[t%SHA_BUFF_COUNT] = rol(tmp,1);\r
+// //HDCP_DEBUG_PRINTF(("w[%2d] = %08lX\n",t,w[t%SHA_BUFF_COUNT]));\r
+// }\r
+//\r
+// if((t>=0)&&(t<20)) {\r
+// tmp = rol(h[0],5) + ((h[1] & h[2]) | (h[3] & ~h[1])) + h[4] + w[t%SHA_BUFF_COUNT] + 0x5a827999;\r
+// //HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+//\r
+// h[4] = h[3];\r
+// h[3] = h[2];\r
+// h[2] = rol(h[1],30);\r
+// h[1] = h[0];\r
+// h[0] = tmp;\r
+//\r
+// }\r
+// if((t>=20)&&(t<40)) {\r
+// tmp = rol(h[0],5) + (h[1] ^ h[2] ^ h[3]) + h[4] + w[t%SHA_BUFF_COUNT] + 0x6ed9eba1;\r
+// //HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+// h[4] = h[3];\r
+// h[3] = h[2];\r
+// h[2] = rol(h[1],30);\r
+// h[1] = h[0];\r
+// h[0] = tmp;\r
+// }\r
+// if((t>=40)&&(t<60)) {\r
+// tmp = rol(h[0], 5) + ((h[1] & h[2]) | (h[1] & h[3]) | (h[2] & h[3])) + h[4] + w[t%SHA_BUFF_COUNT] +\r
+// 0x8f1bbcdc;\r
+// //HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+// h[4] = h[3];\r
+// h[3] = h[2];\r
+// h[2] = rol(h[1],30);\r
+// h[1] = h[0];\r
+// h[0] = tmp;\r
+// }\r
+// if((t>=60)&&(t<80)) {\r
+// tmp = rol(h[0],5) + (h[1] ^ h[2] ^ h[3]) + h[4] + w[t%SHA_BUFF_COUNT] + 0xca62c1d6;\r
+// //HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+// h[4] = h[3];\r
+// h[3] = h[2];\r
+// h[2] = rol(h[1],30);\r
+// h[1] = h[0];\r
+// h[0] = tmp;\r
+// }\r
+// }\r
+// HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+//\r
+// h[0] += 0x67452301 ;\r
+// h[1] += 0xefcdab89;\r
+// h[2] += 0x98badcfe;\r
+// h[3] += 0x10325476;\r
+// h[4] += 0xc3d2e1f0;\r
+// // HDCP_DEBUG_PRINTF(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+// }\r
+//\r
+// /* ----------------------------------------------------------------------\r
+// * Outer SHA algorithm: take an arbitrary length byte string,\r
+// * convert it into 16-word blocks with the prescribed padding at\r
+// * the end,and pass those blocks to the core SHA algorithm.\r
+// */\r
+//\r
+// void SHA_Simple(void *p,LONG len,BYTE *output)\r
+// {\r
+// // SHA_State s;\r
+// int i, t ;\r
+// ULONG c ;\r
+// char *pBuff = p ;\r
+//\r
+// for(i=0;i < len;i+=4)\r
+// {\r
+//\r
+// t=i/4;\r
+// w[t]=0;\r
+// *((char *)&c)= pBuff[i];\r
+// *((char *)&c+1)= pBuff[i+1];\r
+// *((char *)&c+2)= pBuff[i+2];\r
+// *((char *)&c+3)= pBuff[i+3];\r
+// w[t]=c;\r
+// }\r
+//\r
+// c=0x80;\r
+// c<<=((3-len%4)*8);\r
+// w[t] |= c;\r
+//\r
+// /*\r
+// for( i = 0 ; i < len ; i++ )\r
+// {\r
+// t = i/4 ;\r
+// if( i%4 == 0 )\r
+// {\r
+// w[t] = 0 ;\r
+// }\r
+// c = pBuff[i] ;\r
+// c &= 0xFF ;\r
+// c <<= (3-(i%4))*8 ;\r
+// w[t] |= c ;\r
+// // HDCP_DEBUG_PRINTF(("pBuff[%d] = %02x, c = %08lX, w[%d] = %08lX\n",i,pBuff[i],c,t,w[t]));\r
+// }\r
+//\r
+// t = i/4 ;\r
+// if( i%4 == 0 )\r
+// {\r
+// w[t] = 0 ;\r
+// }\r
+// c = 0x80;\r
+// c <<= ((3-i%4)*8);\r
+// w[t]|= c ;\r
+// */\r
+// t++ ;\r
+// for( ; t < 15 ; t++ )\r
+// {\r
+// w[t] = 0 ;\r
+// }\r
+// w[15] = len*8 ;\r
+//\r
+// for( t = 0 ; t< 16 ; t++ )\r
+// {\r
+// HDCP_DEBUG_PRINTF(("w[%2d] = %08lX\n",t,w[t]));\r
+// }\r
+//\r
+// SHATransform(sha);\r
+//\r
+// for( i = 0 ; i < 5 ; i++ )\r
+// {\r
+// output[i*4] = (BYTE)(sha[i]&0xFF);\r
+// output[i*4+1] = (BYTE)((sha[i]>>8)&0xFF);\r
+// output[i*4+2] = (BYTE)((sha[i]>>16)&0xFF);\r
+// output[i*4+3] = (BYTE)((sha[i]>>24)&0xFF);\r
+// }\r
+// }\r
+#endif // 0\r
+\r
+#ifdef SUPPORT_SHA\r
+\r
+SYS_STATUS hdmitx_hdcp_CheckSHA(BYTE pM0[],USHORT BStatus,BYTE pKSVList[],int cDownStream,BYTE Vr[])\r
+{\r
+ int i,n ;\r
+\r
+ for(i = 0 ; i < cDownStream*5 ; i++)\r
+ {\r
+ SHABuff[i] = pKSVList[i] ;\r
+ }\r
+ SHABuff[i++] = BStatus & 0xFF ;\r
+ SHABuff[i++] = (BStatus>>8) & 0xFF ;\r
+ for(n = 0 ; n < 8 ; n++,i++)\r
+ {\r
+ SHABuff[i] = pM0[n] ;\r
+ }\r
+ n = i ;\r
+ // SHABuff[i++] = 0x80 ; // end mask\r
+ for(; i < 64 ; i++)\r
+ {\r
+ SHABuff[i] = 0 ;\r
+ }\r
+ // n = cDownStream * 5 + 2 /* for BStatus */ + 8 /* for M0 */ ;\r
+ // n *= 8 ;\r
+ // SHABuff[62] = (n>>8) & 0xff ;\r
+ // SHABuff[63] = (n>>8) & 0xff ;\r
+/*\r
+ for(i = 0 ; i < 64 ; i++)\r
+ {\r
+ if(i % 16 == 0)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("SHA[]: "));\r
+ }\r
+ HDCP_DEBUG_PRINTF((" %02X",SHABuff[i]));\r
+ if((i%16)==15)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("\n"));\r
+ }\r
+ }\r
+ */\r
+ //SHA_Simple(SHABuff,n,V);\r
+ for(i = 0 ; i < 20 ; i++)\r
+ {\r
+ if(V[i] != Vr[i])\r
+ {\r
+ HDCP_DEBUG_PRINTF(("V[] ="));\r
+ for(i = 0 ; i < 20 ; i++)\r
+ {\r
+ HDCP_DEBUG_PRINTF((" %02X",(int)V[i]));\r
+ }\r
+ HDCP_DEBUG_PRINTF(("\nVr[] ="));\r
+ for(i = 0 ; i < 20 ; i++)\r
+ {\r
+ HDCP_DEBUG_PRINTF((" %02X",(int)Vr[i]));\r
+ }\r
+ return ER_FAIL ;\r
+ }\r
+ }\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+#endif // SUPPORT_SHA\r
+\r
+SYS_STATUS hdmitx_hdcp_GetKSVList(BYTE *pKSVList,BYTE cDownStream)\r
+{\r
+ BYTE TimeOut = 100 ;\r
+ BYTE ucdata ;\r
+\r
+ if( cDownStream == 0 )\r
+ {\r
+ return ER_SUCCESS ;\r
+ }\r
+ if( /* cDownStream == 0 || */ pKSVList == NULL)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_HEADER,0x74);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQOFF,0x43);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQCOUNT,cDownStream * 5);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);\r
+\r
+ for(TimeOut = 200 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+ if(ucdata & B_TX_DDC_DONE)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetKSVList(): DDC Done.\n"));\r
+ break ;\r
+ }\r
+ if(ucdata & B_TX_DDC_ERROR)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetKSVList(): DDC Fail by REG_TX_DDC_STATUS = %x.\n",ucdata));\r
+ return ER_FAIL ;\r
+ }\r
+ delay1ms(5);\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetKSVList(): KSV"));\r
+ for(TimeOut = 0 ; TimeOut < cDownStream * 5 ; TimeOut++)\r
+ {\r
+ pKSVList[TimeOut] = HDMITX_ReadI2C_Byte(REG_TX_DDC_READFIFO);\r
+ HDCP_DEBUG_PRINTF((" %02X",(int)pKSVList[TimeOut]));\r
+ }\r
+ HDCP_DEBUG_PRINTF(("\n"));\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+SYS_STATUS hdmitx_hdcp_GetVr(BYTE *pVr)\r
+{\r
+ BYTE TimeOut ;\r
+ BYTE ucdata ;\r
+\r
+ if(pVr == NULL)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHOST);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_HEADER,0x74);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQOFF,0x20);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_REQCOUNT,20);\r
+ HDMITX_WriteI2C_Byte(REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);\r
+\r
+ for(TimeOut = 200 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ ucdata = HDMITX_ReadI2C_Byte(REG_TX_DDC_STATUS);\r
+ if(ucdata & B_TX_DDC_DONE)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetVr(): DDC Done.\n"));\r
+ break ;\r
+ }\r
+ if(ucdata & B_TX_DDC_ERROR)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetVr(): DDC fail by REG_TX_DDC_STATUS = %x.\n",(int)ucdata));\r
+ return ER_FAIL ;\r
+ }\r
+ delay1ms(5);\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_GetVr(): DDC fail by timeout.\n"));\r
+ return ER_FAIL ;\r
+ }\r
+ Switch_HDMITX_Bank(0);\r
+\r
+ for(TimeOut = 0 ; TimeOut < 5 ; TimeOut++)\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL ,TimeOut);\r
+ pVr[TimeOut*4] = (ULONG)HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE1);\r
+ pVr[TimeOut*4+1] = (ULONG)HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE2);\r
+ pVr[TimeOut*4+2] = (ULONG)HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE3);\r
+ pVr[TimeOut*4+3] = (ULONG)HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE4);\r
+// HDCP_DEBUG_PRINTF(("V' = %02X %02X %02X %02X\n",(int)pVr[TimeOut*4],(int)pVr[TimeOut*4+1],(int)pVr[TimeOut*4+2],(int)pVr[TimeOut*4+3]));\r
+ }\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+SYS_STATUS hdmitx_hdcp_GetM0(BYTE *pM0)\r
+{\r
+ int i ;\r
+\r
+ if(!pM0)\r
+ {\r
+ return ER_FAIL ;\r
+ }\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL,5); // read m0[31:0] from reg51~reg54\r
+ pM0[0] = HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE1);\r
+ pM0[1] = HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE2);\r
+ pM0[2] = HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE3);\r
+ pM0[3] = HDMITX_ReadI2C_Byte(REG_TX_SHA_RD_BYTE4);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL,0); // read m0[39:32] from reg55\r
+ pM0[4] = HDMITX_ReadI2C_Byte(REG_TX_AKSV_RD_BYTE5);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL,1); // read m0[47:40] from reg55\r
+ pM0[5] = HDMITX_ReadI2C_Byte(REG_TX_AKSV_RD_BYTE5);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL,2); // read m0[55:48] from reg55\r
+ pM0[6] = HDMITX_ReadI2C_Byte(REG_TX_AKSV_RD_BYTE5);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SHA_SEL,3); // read m0[63:56] from reg55\r
+ pM0[7] = HDMITX_ReadI2C_Byte(REG_TX_AKSV_RD_BYTE5);\r
+\r
+ HDCP_DEBUG_PRINTF(("M[] ="));\r
+ for(i = 0 ; i < 8 ; i++)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("0x%02x,",(int)pM0[i]));\r
+ }\r
+ HDCP_DEBUG_PRINTF(("\n"));\r
+ return ER_SUCCESS ;\r
+}\r
+\r
+SYS_STATUS hdmitx_hdcp_Authenticate_Repeater()\r
+{\r
+ BYTE uc ,ii;\r
+ // BYTE revoked ;\r
+ // int i ;\r
+ BYTE cDownStream ;\r
+\r
+ BYTE BCaps;\r
+ USHORT BStatus ;\r
+ USHORT TimeOut ;\r
+\r
+ HDCP_DEBUG_PRINTF(("Authentication for repeater\n"));\r
+ // emily add for test,abort HDCP\r
+ // 2007/10/01 marked by jj_tseng@chipadvanced.com\r
+ // HDMITX_WriteI2C_Byte(0x20,0x00);\r
+ // HDMITX_WriteI2C_Byte(0x04,0x01);\r
+ // HDMITX_WriteI2C_Byte(0x10,0x01);\r
+ // HDMITX_WriteI2C_Byte(0x15,0x0F);\r
+ // delay1ms(100);\r
+ // HDMITX_WriteI2C_Byte(0x04,0x00);\r
+ // HDMITX_WriteI2C_Byte(0x10,0x00);\r
+ // HDMITX_WriteI2C_Byte(0x20,0x01);\r
+ // delay1ms(100);\r
+ // test07 = HDMITX_ReadI2C_Byte(0x7);\r
+ // test06 = HDMITX_ReadI2C_Byte(0x6);\r
+ // test08 = HDMITX_ReadI2C_Byte(0x8);\r
+ //~jj_tseng@chipadvanced.com\r
+ // end emily add for test\r
+ //////////////////////////////////////\r
+ // Authenticate Fired\r
+ //////////////////////////////////////\r
+\r
+ hdmitx_hdcp_GetBCaps(&BCaps,&BStatus);\r
+ delay1ms(2);\r
+ if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1))\r
+ {\r
+ HDCP_DEBUG_PRINTF(("HPD Before Fire Auth\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ hdmitx_hdcp_Auth_Fire();\r
+ //delay1ms(550); // emily add for test\r
+ for(ii=0;ii<55;ii++) //delay1ms(550); // emily add for test\r
+ {\r
+ if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1))\r
+ {\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ delay1ms(10);\r
+ }\r
+ for(TimeOut = /*250*6*/10 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("TimeOut = %d wait part 1\n",TimeOut));\r
+ if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1))\r
+ {\r
+ HDCP_DEBUG_PRINTF(("HPD at wait part 1\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1);\r
+ if(uc & B_TX_INT_DDC_BUS_HANG)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("DDC Bus hang\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ uc = HDMITX_ReadI2C_Byte(REG_TX_INT_STAT2);\r
+\r
+ if(uc & B_TX_INT_AUTH_FAIL)\r
+ {\r
+ /*\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR0,B_TX_CLR_AUTH_FAIL);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR1,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,B_TX_INTACTDONE);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,0);\r
+ */\r
+ HDCP_DEBUG_PRINTF(("hdmitx_hdcp_Authenticate_Repeater(): B_TX_INT_AUTH_FAIL.\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ // emily add for test\r
+ // test =(HDMITX_ReadI2C_Byte(0x7)&0x4)>>2 ;\r
+ if(uc & B_TX_INT_KSVLIST_CHK)\r
+ {\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR0,B_TX_CLR_KSVLISTCHK);\r
+ HDMITX_WriteI2C_Byte(REG_TX_INT_CLR1,0);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,B_TX_INTACTDONE);\r
+ HDMITX_WriteI2C_Byte(REG_TX_SYS_STATUS,0);\r
+ HDCP_DEBUG_PRINTF(("B_TX_INT_KSVLIST_CHK\n"));\r
+ break ;\r
+ }\r
+ delay1ms(5);\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("Time out for wait KSV List checking interrupt\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ ///////////////////////////////////////\r
+ // clear KSVList check interrupt.\r
+ ///////////////////////////////////////\r
+\r
+ for(TimeOut = 500 ; TimeOut > 0 ; TimeOut --)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("TimeOut=%d at wait FIFO ready\n",TimeOut));\r
+ if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1))\r
+ {\r
+ HDCP_DEBUG_PRINTF(("HPD at wait FIFO ready\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ if(hdmitx_hdcp_GetBCaps(&BCaps,&BStatus) == ER_FAIL)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("Get BCaps fail\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ if(BCaps & B_TX_CAP_KSV_FIFO_RDY)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("FIFO Ready\n"));\r
+ break ;\r
+ }\r
+ delay1ms(5);\r
+\r
+ }\r
+ if(TimeOut == 0)\r
+ {\r
+ HDCP_DEBUG_PRINTF(("Get KSV FIFO ready TimeOut\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ HDCP_DEBUG_PRINTF(("Wait timeout = %d\n",TimeOut));\r
+\r
+ hdmitx_ClearDDCFIFO();\r
+ hdmitx_GenerateDDCSCLK();\r
+ cDownStream = (BStatus & M_TX_DOWNSTREAM_COUNT);\r
+\r
+ if(/*cDownStream == 0 ||*/ cDownStream > 6 || BStatus & (B_TX_MAX_CASCADE_EXCEEDED|B_TX_DOWNSTREAM_OVER))\r
+ {\r
+ HDCP_DEBUG_PRINTF(("Invalid Down stream count,fail\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+#ifdef SUPPORT_SHA\r
+ if(hdmitx_hdcp_GetKSVList(KSVList,cDownStream) == ER_FAIL)\r
+ {\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+#if 0\r
+ for(i = 0 ; i < cDownStream ; i++)\r
+ {\r
+ revoked=FALSE ; uc = 0 ;\r
+ for( TimeOut = 0 ; TimeOut < 5 ; TimeOut++ )\r
+ {\r
+ // check bit count\r
+ uc += countbit(KSVList[i*5+TimeOut]);\r
+ }\r
+ if( uc != 20 ) revoked = TRUE ;\r
+\r
+ if(revoked)\r
+ {\r
+// HDCP_DEBUG_PRINTF(("KSVFIFO[%d] = %02X %02X %02X %02X %02X is revoked\n",i,(int)KSVList[i*5],(int)KSVList[i*5+1],(int)KSVList[i*5+2],(int)KSVList[i*5+3],(int)KSVList[i*5+4]));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ }\r
+#endif\r
+\r
+ if(hdmitx_hdcp_GetVr(Vr) == ER_FAIL)\r
+ {\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ if(hdmitx_hdcp_GetM0(M0) == ER_FAIL)\r
+ {\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ // do check SHA\r
+ if(hdmitx_hdcp_CheckSHA(M0,BStatus,KSVList,cDownStream,Vr) == ER_FAIL)\r
+ {\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+ if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&HDMITX_ReadI2C_Byte(REG_TX_INT_STAT1))\r
+ {\r
+ HDCP_DEBUG_PRINTF(("HPD at Final\n"));\r
+ goto hdmitx_hdcp_Repeater_Fail ;\r
+ }\r
+#endif // SUPPORT_SHA\r
+\r
+ hdmitx_hdcp_ResumeRepeaterAuthenticate();\r
+ hdmiTxDev[0].bAuthenticated = TRUE ;\r
+ return ER_SUCCESS ;\r
+\r
+hdmitx_hdcp_Repeater_Fail:\r
+ hdmitx_hdcp_CancelRepeaterAuthenticate();\r
+ return ER_FAIL ;\r
+}\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// Function: hdmitx_hdcp_ResumeAuthentication\r
+// Parameter: N/A\r
+// Return: N/A\r
+// Remark: called by interrupt handler to restart Authentication and Encryption.\r
+// Side-Effect: as Authentication and Encryption.\r
+//////////////////////////////////////////////////////////////////////\r
+\r
+void hdmitx_hdcp_ResumeAuthentication()\r
+{\r
+ setHDMITX_AVMute(TRUE);\r
+ if(hdmitx_hdcp_Authenticate() == ER_SUCCESS)\r
+ {\r
+ }\r
+ setHDMITX_AVMute(FALSE);\r
+}\r
+\r
+#endif // SUPPORT_HDCP\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_hdcp.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#ifndef _HDMITX_HDCP_H_\r
+#define _HDMITX_HDCP_H_\r
+\r
+\r
+#define REG_TX_HDCP_DESIRE 0x20\r
+ #define B_TX_ENABLE_HDPC11 (1<<1)\r
+ #define B_TX_CPDESIRE (1<<0)\r
+\r
+#define REG_TX_AUTHFIRE 0x21\r
+#define REG_TX_LISTCTRL 0x22\r
+ #define B_TX_LISTFAIL (1<<1)\r
+ #define B_TX_LISTDONE (1<<0)\r
+\r
+#define REG_TX_AKSV 0x23\r
+#define REG_TX_AKSV0 0x23\r
+#define REG_TX_AKSV1 0x24\r
+#define REG_TX_AKSV2 0x25\r
+#define REG_TX_AKSV3 0x26\r
+#define REG_TX_AKSV4 0x27\r
+\r
+#define REG_TX_AN 0x28\r
+#define REG_TX_AN_GEN 0x30\r
+#define REG_TX_ARI 0x38\r
+#define REG_TX_ARI0 0x38\r
+#define REG_TX_ARI1 0x39\r
+#define REG_TX_APJ 0x3A\r
+\r
+#define REG_TX_BKSV 0x3B\r
+#define REG_TX_BRI 0x40\r
+#define REG_TX_BRI0 0x40\r
+#define REG_TX_BRI1 0x41\r
+#define REG_TX_BPJ 0x42\r
+#define REG_TX_BCAP 0x43\r
+ #define B_TX_CAP_HDMI_REPEATER (1<<6)\r
+ #define B_TX_CAP_KSV_FIFO_RDY (1<<5)\r
+ #define B_TX_CAP_HDMI_FAST_MODE (1<<4)\r
+ #define B_CAP_HDCP_1p1 (1<<1)\r
+ #define B_TX_CAP_FAST_REAUTH (1<<0)\r
+#define REG_TX_BSTAT 0x44\r
+#define REG_TX_BSTAT0 0x44\r
+#define REG_TX_BSTAT1 0x45\r
+ #define B_TX_CAP_HDMI_MODE (1<<12)\r
+ #define B_TX_CAP_DVI_MODE (0<<12)\r
+ #define B_TX_MAX_CASCADE_EXCEEDED (1<<11)\r
+ #define M_TX_REPEATER_DEPTH (0x7<<8)\r
+ #define O_TX_REPEATER_DEPTH 8\r
+ #define B_TX_DOWNSTREAM_OVER (1<<7)\r
+ #define M_TX_DOWNSTREAM_COUNT 0x7F\r
+\r
+#define REG_TX_AUTH_STAT 0x46\r
+#define B_TX_AUTH_DONE (1<<7)\r
+////////////////////////////////////////////////////\r
+// Function Prototype\r
+////////////////////////////////////////////////////\r
+\r
+BOOL getHDMITX_AuthenticationDone();\r
+void hdmitx_hdcp_ClearAuthInterrupt();\r
+void hdmitx_hdcp_ResetAuth();\r
+void hdmitx_hdcp_Auth_Fire();\r
+void hdmitx_hdcp_StartAnCipher();\r
+void hdmitx_hdcp_StopAnCipher();\r
+void hdmitx_hdcp_GenerateAn();\r
+SYS_STATUS hdmitx_hdcp_GetBCaps(PBYTE pBCaps ,PUSHORT pBStatus);\r
+SYS_STATUS hdmitx_hdcp_GetBKSV(BYTE *pBKSV);\r
+\r
+void hdmitx_hdcp_Reset();\r
+SYS_STATUS hdmitx_hdcp_Authenticate();\r
+SYS_STATUS hdmitx_hdcp_VerifyIntegration();\r
+void hdmitx_hdcp_CancelRepeaterAuthenticate();\r
+void hdmitx_hdcp_ResumeRepeaterAuthenticate();\r
+SYS_STATUS hdmitx_hdcp_CheckSHA(BYTE pM0[],USHORT BStatus,BYTE pKSVList[],int cDownStream,BYTE Vr[]);\r
+SYS_STATUS hdmitx_hdcp_GetKSVList(BYTE *pKSVList,BYTE cDownStream);\r
+SYS_STATUS hdmitx_hdcp_GetVr(BYTE *pVr);\r
+SYS_STATUS hdmitx_hdcp_GetM0(BYTE *pM0);\r
+SYS_STATUS hdmitx_hdcp_Authenticate_Repeater();\r
+void hdmitx_hdcp_ResumeAuthentication();\r
+#endif // _HDMITX_HDCP_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_input.c>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#include "hdmitx.h"\r
+#include "hdmitx_drv.h"\r
+\r
+#ifdef HDMITX_INPUT_INFO\r
+extern HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT] ;\r
+\r
+LONG CalcRCLK();\r
+LONG CalcAudFS();\r
+LONG CalcRCLK();\r
+\r
+#define InitCEC() HDMITX_SetI2C_Byte(0x0F, 0x08, 0x00)\r
+#define DisableCEC() HDMITX_SetI2C_Byte(0x0F, 0x08, 0x08)\r
+\r
+LONG CalcAudFS()\r
+{\r
+ // LONG RCLK ;\r
+ LONG Cnt ;\r
+ LONG FS ;\r
+\r
+ // RCLK = CalcRCLK();\r
+ Switch_HDMITX_Bank(0);\r
+ Cnt = (LONG)HDMITX_ReadI2C_Byte(0x60);\r
+ FS = hdmiTxDev[0].RCLK / 2 ;\r
+ FS /= Cnt ;\r
+ HDMITX_DEBUG_PRINTF1(("FS = %ld RCLK = %ld, Cnt = %ld\n",FS,hdmiTxDev[0].RCLK,Cnt)) ;\r
+ return FS ;\r
+}\r
+\r
+LONG CalcPCLK()\r
+{\r
+ BYTE uc, div ;\r
+ int i ;\r
+ long sum , count, PCLK ;\r
+\r
+ Switch_HDMITX_Bank(0);\r
+ uc = HDMITX_ReadI2C_Byte(0x5F) & 0x80 ;\r
+\r
+ if( ! uc )\r
+ {\r
+ return 0 ;\r
+ }\r
+ // InitCEC();\r
+ // // uc = CEC_ReadI2C_Byte(0x09) & 0xFE ;\r
+ // CEC_WriteI2C_Byte(0x09, 1);\r
+ // delay1ms(100);\r
+ // CEC_WriteI2C_Byte(0x09, 0);\r
+ // RCLK = CEC_ReadI2C_Byte(0x47);\r
+ // RCLK <<= 8 ;\r
+ // RCLK |= CEC_ReadI2C_Byte(0x46);\r
+ // RCLK <<= 8 ;\r
+ // RCLK |= CEC_ReadI2C_Byte(0x45);\r
+ // DisableCEC();\r
+ // // RCLK *= 160 ; // RCLK /= 100 ;\r
+ // // RCLK in KHz.\r
+\r
+ HDMITX_SetI2C_Byte(0xD7, 0xF0, 0x80);\r
+ delay1ms(1);\r
+ HDMITX_SetI2C_Byte(0xD7, 0x80, 0x00);\r
+\r
+ count = HDMITX_ReadI2C_Byte(0xD7) & 0xF ;\r
+ count <<= 8 ;\r
+ count |= HDMITX_ReadI2C_Byte(0xD8);\r
+\r
+ for( div = 7 ; div > 0 ; div-- )\r
+ {\r
+ // printf("div = %d\n",(int)div) ;\r
+ if(count < (1<<(11-div)) )\r
+ {\r
+ break ;\r
+ }\r
+ }\r
+ HDMITX_SetI2C_Byte(0xD7, 0x70, div<<4);\r
+\r
+ uc = HDMITX_ReadI2C_Byte(0xD7) & 0x7F ;\r
+ for( i = 0 , sum = 0 ; i < 100 ; i ++ )\r
+ {\r
+ HDMITX_WriteI2C_Byte(0xD7, uc|0x80) ;\r
+ delay1ms(1);\r
+ HDMITX_WriteI2C_Byte(0xD7, uc) ;\r
+\r
+ count = HDMITX_ReadI2C_Byte(0xD7) & 0xF ;\r
+ count <<= 8 ;\r
+ count |= HDMITX_ReadI2C_Byte(0xD8);\r
+ sum += count ;\r
+ }\r
+ sum /= 100 ; count = sum ;\r
+\r
+ HDMITX_DEBUG_PRINTF1(("RCLK(in GetPCLK) = %ld\n",hdmiTxDev[0].RCLK));\r
+ HDMITX_DEBUG_PRINTF1(("div = %d, count = %d\n",(int)div,(int)count) );\r
+ HDMITX_DEBUG_PRINTF1(("count = %ld\n",count) );\r
+\r
+ PCLK = hdmiTxDev[0].RCLK * 128 / count * 16 ;\r
+ PCLK *= (1<<div);\r
+\r
+ if( HDMITX_ReadI2C_Byte(0x70) & 0x10 )\r
+ {\r
+ PCLK /= 2 ;\r
+ }\r
+\r
+ HDMITX_DEBUG_PRINTF1(("PCLK = %ld\n",PCLK) );\r
+ return PCLK ;\r
+}\r
+\r
+LONG CalcRCLK()\r
+{\r
+ // BYTE uc ;\r
+ int i ;\r
+ long sum, RCLKCNT ;\r
+\r
+ InitCEC();\r
+ sum = 0 ;\r
+ for( i = 0 ; i < 5 ; i++ )\r
+ {\r
+ // uc = CEC_ReadI2C_Byte(0x09) & 0xFE ;\r
+ CEC_WriteI2C_Byte(0x09, 1);\r
+ delay1ms(100);\r
+ CEC_WriteI2C_Byte(0x09, 0);\r
+ RCLKCNT = CEC_ReadI2C_Byte(0x47);\r
+ RCLKCNT <<= 8 ;\r
+ RCLKCNT |= CEC_ReadI2C_Byte(0x46);\r
+ RCLKCNT <<= 8 ;\r
+ RCLKCNT |= CEC_ReadI2C_Byte(0x45);\r
+ // HDMITX_DEBUG_PRINTF1(("RCLK = %ld\n",RCLKCNT) );\r
+ sum += RCLKCNT ;\r
+ }\r
+ DisableCEC();\r
+ RCLKCNT = sum * 32 ;\r
+ HDMITX_DEBUG_PRINTF(("RCLK = %ld,%03ld,%03ld\n",RCLKCNT/1000000,(RCLKCNT%1000000)/1000,RCLKCNT%1000));\r
+ return RCLKCNT ;\r
+}\r
+\r
+USHORT hdmitx_getInputHTotal()\r
+{\r
+ BYTE uc ;\r
+ USHORT hTotal ;\r
+ HDMITX_SetI2C_Byte(0x0F,1,0) ;\r
+ HDMITX_SetI2C_Byte(0xA8,8,8) ;\r
+\r
+ uc = HDMITX_ReadI2C_Byte(0xB2) ;\r
+ hTotal = (uc&1)?(1<<12):0 ;\r
+ uc = HDMITX_ReadI2C_Byte(0x91) ;\r
+ hTotal |= ((USHORT)uc)<<4 ;\r
+ uc = HDMITX_ReadI2C_Byte(0x90) ;\r
+ hTotal |= (uc&0xF0) >> 4 ;\r
+ HDMITX_SetI2C_Byte(0xA8,8,0) ;\r
+ return hTotal ;\r
+}\r
+\r
+USHORT hdmitx_getInputVTotal()\r
+{\r
+ BYTE uc ;\r
+ USHORT vTotal ;\r
+ HDMITX_SetI2C_Byte(0x0F,1,0) ;\r
+ HDMITX_SetI2C_Byte(0xA8,8,8) ;\r
+\r
+ uc = HDMITX_ReadI2C_Byte(0x99) ;\r
+ vTotal = ((USHORT)uc&0xF)<<8 ;\r
+ uc = HDMITX_ReadI2C_Byte(0x98) ;\r
+ vTotal |= uc;\r
+ HDMITX_SetI2C_Byte(0xA8,8,0) ;\r
+ return vTotal ;\r
+}\r
+\r
+BOOL hdmitx_isInputInterlace()\r
+{\r
+ BYTE uc ;\r
+\r
+ HDMITX_SetI2C_Byte(0x0F,1,0) ;\r
+ HDMITX_SetI2C_Byte(0xA8,8,8) ;\r
+\r
+ uc = HDMITX_ReadI2C_Byte(0xA5) ;\r
+ HDMITX_SetI2C_Byte(0xA8,8,0) ;\r
+ return uc&(1<<4)?TRUE:FALSE ;\r
+}\r
+\r
+BYTE hdmitx_getAudioCount()\r
+{\r
+ return HDMITX_ReadI2C_Byte(REG_TX_AUD_COUNT) ;\r
+}\r
+#endif\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_input.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+#ifndef _HDMITX_DEBUG_H_\r
+#define _HDMITX_DEBUG_H_\r
+\r
+\r
+#ifdef HDMITX_INPUT_INFO\r
+LONG CalcPCLK();\r
+LONG CalcAudFS();\r
+LONG CalcRCLK();\r
+BYTE hdmitx_getAudioCount() ;\r
+\r
+USHORT hdmitx_getInputHTotal();\r
+USHORT hdmitx_getInputVTotal();\r
+BOOL hdmitx_isInputInterlace();\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_sys.c>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// This is the sample program for CAT6611 driver usage.\r
+///////////////////////////////////////////////////////////////////////////////\r
+#include <linux/kernel.h>\r
+#include <linux/delay.h>\r
+\r
+#include "hdmitx.h"\r
+#include "hdmitx_sys.h"\r
+\r
+_CODE HDMITXDEV InstanceData =\r
+{\r
+\r
+ 0, // BYTE I2C_DEV ;\r
+ HDMI_TX_I2C_SLAVE_ADDR, // BYTE I2C_ADDR ;\r
+\r
+ /////////////////////////////////////////////////\r
+ // Interrupt Type\r
+ /////////////////////////////////////////////////\r
+ 0x40, // BYTE bIntType ; // = 0 ;\r
+ /////////////////////////////////////////////////\r
+ // Video Property\r
+ /////////////////////////////////////////////////\r
+ INPUT_SIGNAL_TYPE ,// BYTE bInputVideoSignalType ; // for Sync Embedded,CCIR656,InputDDR\r
+\r
+ /////////////////////////////////////////////////\r
+ // Audio Property\r
+ /////////////////////////////////////////////////\r
+ I2S_FORMAT, // BYTE bOutputAudioMode ; // = 0 ;\r
+ FALSE , // BYTE bAudioChannelSwap ; // = 0 ;\r
+ 0x01, // BYTE bAudioChannelEnable ;\r
+ INPUT_SAMPLE_FREQ ,// BYTE bAudFs ;\r
+ 0, // unsigned long TMDSClock ;\r
+ FALSE, // BYTE bAuthenticated:1 ;\r
+ FALSE, // BYTE bHDMIMode: 1;\r
+ FALSE, // BYTE bIntPOL:1 ; // 0 = Low Active\r
+ FALSE, // BYTE bHPD:1 ;\r
+};\r
+\r
+#ifdef HDMITX_INPUT_INFO\r
+// HDMI_VTiming currVTiming ;\r
+////////////////////////////////////////////////////////////////////////////////\r
+// HDMI VTable\r
+////////////////////////////////////////////////////////////////////////////////\r
+static HDMI_VTiming _CODE s_VMTable[] = {\r
+\r
+ { 1,0,640,480,800,525,25175000L,0x89,16,96,48,10,2,33,PROG,Vneg,Hneg},//640x480@60Hz\r
+ { 2,0,720,480,858,525,27000000L,0x80,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@60Hz\r
+ { 3,0,720,480,858,525,27000000L,0x80,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@60Hz\r
+ { 4,0,1280,720,1650,750,74250000L,0x2E,110,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@60Hz\r
+ { 5,0,1920,540,2200,562,74250000L,0x2E,88,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@60Hz\r
+ { 6,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz\r
+ { 7,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz\r
+ { 8,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz\r
+ { 9,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz\r
+ {10,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz\r
+ {11,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz\r
+ {12,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz\r
+ {13,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz\r
+ {14,1,1440,480,1716,525,54000000L,0x40,32,124,120,9,6,30,PROG,Vneg,Hneg},//1440x480@60Hz\r
+ {15,1,1440,480,1716,525,54000000L,0x40,32,124,120,9,6,30,PROG,Vneg,Hneg},//1440x480@60Hz\r
+ {16,0,1920,1080,2200,1125,148500000L,0x17,88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@60Hz\r
+ {17,0,720,576,864,625,27000000L,0x80,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@50Hz\r
+ {18,0,720,576,864,625,27000000L,0x80,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@50Hz\r
+ {19,0,1280,720,1980,750,74250000L,0x2E,440,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@50Hz\r
+ {20,0,1920,540,2640,562,74250000L,0x2E,528,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@50Hz\r
+ {21,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz\r
+ {22,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz\r
+ {23,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz\r
+ {24,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz\r
+ {25,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz\r
+ {26,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz\r
+ {27,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz\r
+ {28,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz\r
+ {29,1,1440,576,1728,625,54000000L,0x40,24,128,136,5,5,39,PROG,Vpos,Hneg},//1440x576@50Hz\r
+ {30,1,1440,576,1728,625,54000000L,0x40,24,128,136,5,5,39,PROG,Vpos,Hneg},//1440x576@50Hz\r
+ {31,0,1920,1080,2640,1125,148500000L,0x17,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@50Hz\r
+ {32,0,1920,1080,2750,1125,74250000L,0x2E,638,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@24Hz\r
+ {33,0,1920,1080,2640,1125,74250000L,0x2E,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@25Hz\r
+ {34,0,1920,1080,2200,1125,74250000L,0x2E,88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@30Hz\r
+\r
+ {35,2,2880,480,1716*2,525,108000000L,0x20,32*2,124*2,120*2,9,6,30,PROG,Vneg,Hneg},//2880x480@60Hz\r
+ {36,2,2880,480,1716*2,525,108000000L,0x20,32*2,124*2,120*2,9,6,30,PROG,Vneg,Hneg},//2880x480@60Hz\r
+ {37,1,2880,576,3456,625,108000000L,0x20,24*2,128*2,136*2,5,5,39,PROG,Vneg,Hneg},//2880x576@50Hz\r
+ {38,2,2880,576,3456,625,108000000L,0x20,24*2,128*2,136*2,5,5,39,PROG,Vneg,Hneg},//2880x576@50Hz\r
+\r
+ {39,0,1920,540,2304,625,72000000L,0x17,32,168,184,23,5,57,INTERLACE,Vneg,Hpos},//1920x1080@50Hz\r
+ // 100Hz\r
+ {40,0,1920,540,2640,562,148500000L,0x17,528,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@100Hz\r
+ {41,0,1280,720,1980,750,148500000L,0x17,440,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@100Hz\r
+ {42,0,720,576,864,625, 54000000L,0x40,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@100Hz\r
+ {43,0,720,576,864,625, 54000000L,0x40,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@100Hz\r
+ {44,1,720,288,864,312, 27000000L,0x80,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@100Hz\r
+ {45,1,720,288,864,312, 27000000L,0x80,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@100Hz\r
+ // 120Hz\r
+ {46,0,1920,540,2200,562,148500000L,0x17,88,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@120Hz\r
+ {47,0,1280,720,1650,750,148500000L,0x17,110,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@120Hz\r
+ {48,0, 720,480, 858,525, 54000000L,0x40,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz\r
+ {49,0, 720,480, 858,525, 54000000L,0x40,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz\r
+ {50,1, 720,240, 858,262, 27000000L,0x80,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz\r
+ {51,1, 720,240, 858,262, 27000000L,0x80,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz\r
+\r
+ // 200Hz\r
+ {52,0,720,576,864,625,108000000L,0x20,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@200Hz\r
+ {53,0,720,576,864,625,108000000L,0x20,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@200Hz\r
+ {54,1,720,288,864,312, 54000000L,0x40,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@200Hz\r
+ {55,1,720,288,864,312, 54000000L,0x40,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@200Hz\r
+ // 240Hz\r
+ {56,0,720,480,858,525,108000000L,0x20,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz\r
+ {57,0,720,480,858,525,108000000L,0x20,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz\r
+ {58,1,720,240,858,262, 54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz\r
+ {59,1,720,240,858,262, 54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz\r
+ // 720p low resolution\r
+ {60,0,1280, 720,3300, 750, 59400000L,0x3A,1760,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@24Hz\r
+ {61,0,1280, 720,3960, 750, 74250000L,0x2E,2420,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@25Hz\r
+ {62,0,1280, 720,3300, 750, 74250000L,0x2E,1760,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@30Hz\r
+ // 1080p high refresh rate\r
+ {63,0,1920,1080,2200,1125,297000000L,0x0B, 88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@120Hz\r
+ {64,0,1920,1080,2640,1125,297000000L,0x0B,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@100Hz\r
+ // VESA mode\r
+ {0,0,640,350,832,445,31500000L,0x6D,32,64,96,32,3,60,PROG,Vneg,Hpos},// 640x350@85\r
+ {0,0,640,400,832,445,31500000L,0x6D,32,64,96,1,3,41,PROG,Vneg,Hneg},// 640x400@85\r
+ {0,0,832,624,1152,667,57283000L,0x3C,32,64,224,1,3,39,PROG,Vneg,Hneg},// 832x624@75Hz\r
+ {0,0,720,350,900,449,28322000L,0x7A,18,108,54,59,2,38,PROG,Vneg,Hneg},// 720x350@70Hz\r
+ {0,0,720,400,900,449,28322000L,0x7A,18,108,54,13,2,34,PROG,Vpos,Hneg},// 720x400@70Hz\r
+ {0,0,720,400,936,446,35500000L,0x61,36,72,108,1,3,42,PROG,Vpos,Hneg},// 720x400@85\r
+ {0,0,640,480,800,525,25175000L,0x89,16,96,48,10,2,33,PROG,Vneg,Hneg},// 640x480@60\r
+ {0,0,640,480,832,520,31500000L,0x6D,24,40,128,9,3,28,PROG,Vneg,Hneg},// 640x480@72\r
+ {0,0,640,480,840,500,31500000L,0x6D,16,64,120,1,3,16,PROG,Vneg,Hneg},// 640x480@75\r
+ {0,0,640,480,832,509,36000000L,0x60,56,56,80,1,3,25,PROG,Vneg,Hneg},// 640x480@85\r
+ {0,0,800,600,1024,625,36000000L,0x60,24,72,128,1,2,22,PROG,Vpos,Hpos},// 800x600@56\r
+ {0,0,800,600,1056,628,40000000L,0x56,40,128,88,1,4,23,PROG,Vpos,Hpos},// 800x600@60\r
+ {0,0,800,600,1040,666,50000000L,0x45,56,120,64,37,6,23,PROG,Vpos,Hpos},// 800x600@72\r
+ {0,0,800,600,1056,625,49500000L,0x45,16,80,160,1,3,21,PROG,Vpos,Hpos},// 800x600@75\r
+ {0,0,800,600,1048,631,56250000L,0x3D,32,64,152,1,3,27,PROG,Vpos,Hpos},// 800X600@85\r
+ {0,0,848,480,1088,517,33750000L,0x66,16,112,112,6,8,23,PROG,Vpos,Hpos},// 840X480@60\r
+ {0,0,1024,384,1264,408,44900000L,0x4C,8,176,56,0,4,20,INTERLACE,Vpos,Hpos},//1024x768(I)@87Hz\r
+ {0,0,1024,768,1344,806,65000000L,0x35,24,136,160,3,6,29,PROG,Vneg,Hneg},// 1024x768@60\r
+ {0,0,1024,768,1328,806,75000000L,0x2E,24,136,144,3,6,29,PROG,Vneg,Hneg},// 1024x768@70\r
+ {0,0,1024,768,1312,800,78750000L,0x2B,16,96,176,1,3,28,PROG,Vpos,Hpos},// 1024x768@75\r
+ {0,0,1024,768,1376,808,94500000L,0x24,48,96,208,1,3,36,PROG,Vpos,Hpos},// 1024x768@85\r
+ {0,0,1152,864,1600,900,108000000L,0x20,64,128,256,1,3,32,PROG,Vpos,Hpos},// 1152x864@75\r
+ {0,0,1280,768,1440,790,68250000L,0x32,48,32,80,3,7,12,PROG,Vneg,Hpos},// 1280x768@60-R\r
+ {0,0,1280,768,1664,798,79500000L,0x2B,64,128,192,3,7,20,PROG,Vpos,Hneg},// 1280x768@60\r
+ {0,0,1280,768,1696,805,102250000L,0x21,80,128,208,3,7,27,PROG,Vpos,Hneg},// 1280x768@75\r
+ {0,0,1280,768,1712,809,117500000L,0x1D,80,136,216,3,7,31,PROG,Vpos,Hneg},// 1280x768@85\r
+\r
+ {0,0,1280,800,1440, 823, 71000000L,0x31, 48, 32, 80,3,6,14,PROG,Vpos,Hneg},// 1280x800@60Hz\r
+ {0,0,1280,800,1680, 831, 83500000L,0x29, 72,128,200,3,6,22,PROG,Vpos,Hneg},// 1280x800@60Hz\r
+ {0,0,1280,800,1696, 838,106500000L,0x20, 80,128,208,3,6,29,PROG,Vpos,Hneg},// 1280x800@75Hz\r
+ {0,0,1280,800,1712, 843,122500000L,0x1C, 80,136,216,3,6,34,PROG,Vpos,Hneg},// 1280x800@85Hz\r
+\r
+\r
+ {0,0,1280,960,1800,1000,108000000L,0x20,96,112,312,1,3,36,PROG,Vpos,Hpos},// 1280x960@60\r
+ {0,0,1280,960,1728,1011,148500000L,0x17,64,160,224,1,3,47,PROG,Vpos,Hpos},// 1280x960@85\r
+ {0,0,1280,1024,1688,1066,108000000L,0x20,48,112,248,1,3,38,PROG,Vpos,Hpos},// 1280x1024@60\r
+ {0,0,1280,1024,1688,1066,135000000L,0x19,16,144,248,1,3,38,PROG,Vpos,Hpos},// 1280x1024@75\r
+ {0,0,1280,1024,1728,1072,157500000L,0x15,64,160,224,1,3,44,PROG,Vpos,Hpos},// 1280X1024@85\r
+ {0,0,1360,768,1792,795,85500000L,0x28,64,112,256,3,6,18,PROG,Vpos,Hpos},// 1360X768@60\r
+\r
+ {0,0,1366,768,1792,798,85500000L,0x28, 70,143,213,3,3,24,PROG,Vpos,Hpos},// 1366X768@60\r
+ {0,0,1366,768,1500,800,72000000L,0x30, 14, 56, 64,1,3,28,PROG,Vpos,Hpos},// 1360X768@60\r
+ {0,0,1400,1050,1560,1080,101000000L,0x22,48,32,80,3,4,23,PROG,Vneg,Hpos},// 1400x768@60-R\r
+ {0,0,1400,1050,1864,1089,121750000L,0x1C,88,144,232,3,4,32,PROG,Vpos,Hneg},// 1400x768@60\r
+ {0,0,1400,1050,1896,1099,156000000L,0x16,104,144,248,3,4,42,PROG,Vpos,Hneg},// 1400x1050@75\r
+ {0,0,1400,1050,1912,1105,179500000L,0x13,104,152,256,3,4,48,PROG,Vpos,Hneg},// 1400x1050@85\r
+ {0,0,1440,900,1600,926,88750000L,0x26,48,32,80,3,6,17,PROG,Vneg,Hpos},// 1440x900@60-R\r
+ {0,0,1440,900,1904,934,106500000L,0x20,80,152,232,3,6,25,PROG,Vpos,Hneg},// 1440x900@60\r
+ {0,0,1440,900,1936,942,136750000L,0x19,96,152,248,3,6,33,PROG,Vpos,Hneg},// 1440x900@75\r
+ {0,0,1440,900,1952,948,157000000L,0x16,104,152,256,3,6,39,PROG,Vpos,Hneg},// 1440x900@85\r
+ {0,0,1600,1200,2160,1250,162000000L,0x15,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@60\r
+ {0,0,1600,1200,2160,1250,175500000L,0x13,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@65\r
+ {0,0,1600,1200,2160,1250,189000000L,0x12,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@70\r
+ {0,0,1600,1200,2160,1250,202500000L,0x11,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@75\r
+ {0,0,1600,1200,2160,1250,229500000L,0x0F,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@85\r
+ {0,0,1680,1050,1840,1080,119000000L,0x1D,48,32,80,3,6,21,PROG,Vneg,Hpos},// 1680x1050@60-R\r
+ {0,0,1680,1050,2240,1089,146250000L,0x17,104,176,280,3,6,30,PROG,Vpos,Hneg},// 1680x1050@60\r
+ {0,0,1680,1050,2272,1099,187000000L,0x12,120,176,296,3,6,40,PROG,Vpos,Hneg},// 1680x1050@75\r
+ {0,0,1680,1050,2288,1105,214750000L,0x10,128,176,304,3,6,46,PROG,Vpos,Hneg},// 1680x1050@85\r
+ {0,0,1792,1344,2448,1394,204750000L,0x10,128,200,328,1,3,46,PROG,Vpos,Hneg},// 1792x1344@60\r
+ {0,0,1792,1344,2456,1417,261000000L,0x0D,96,216,352,1,3,69,PROG,Vpos,Hneg},// 1792x1344@75\r
+ {0,0,1856,1392,2528,1439,218250000L,0x0F,96,224,352,1,3,43,PROG,Vpos,Hneg},// 1856x1392@60\r
+ {0,0,1856,1392,2560,1500,288000000L,0x0C,128,224,352,1,3,104,PROG,Vpos,Hneg},// 1856x1392@75\r
+ {0,0,1920,1200,2080,1235,154000000L,0x16,48,32,80,3,6,26,PROG,Vneg,Hpos},// 1920x1200@60-R\r
+ {0,0,1920,1200,2592,1245,193250000L,0x11,136,200,336,3,6,36,PROG,Vpos,Hneg},// 1920x1200@60\r
+ {0,0,1920,1200,2608,1255,245250000L,0x0E,136,208,344,3,6,46,PROG,Vpos,Hneg},// 1920x1200@75\r
+ {0,0,1920,1200,2624,1262,281250000L,0x0C,144,208,352,3,6,53,PROG,Vpos,Hneg},// 1920x1200@85\r
+ {0,0,1920,1440,2600,1500,234000000L,0x0E,128,208,344,1,3,56,PROG,Vpos,Hneg},// 1920x1440@60\r
+ {0,0,1920,1440,2640,1500,297000000L,0x0B,144,224,352,1,3,56,PROG,Vpos,Hneg},// 1920x1440@75\r
+};\r
+#define SizeofVMTable (sizeof(s_VMTable)/sizeof(HDMI_VTiming))\r
+\r
+void HDMITX_MonitorInputVideoChange();\r
+void HDMITX_MonitorInputAudioChange();\r
+\r
+#else\r
+#define SizeofVMTable 0\r
+#endif\r
+\r
+#define DIFF(a,b) (((a)>(b))?((a)-(b)):((b)-(a)))\r
+\r
+////////////////////////////////////////////////////////////////////////////////\r
+// EDID\r
+////////////////////////////////////////////////////////////////////////////////\r
+static _XDATA RX_CAP RxCapability ;\r
+static BOOL bChangeMode = FALSE ;\r
+static BOOL bChangeAudio = FALSE ;\r
+\r
+_XDATA unsigned char CommunBuff[128] ;\r
+// _XDATA AVI_InfoFrame AviInfo;\r
+// _XDATA Audio_InfoFrame AudioInfo ;\r
+// _XDATA VendorSpecific_InfoFrame VS_Info;\r
+_CODE BYTE CA[] = { 0,0,0, 02, 0x3, 0x7, 0xB, 0xF, 0x1F } ;\r
+////////////////////////////////////////////////////////////////////////////////\r
+// Program utility.\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+\r
+BYTE bInputColorMode = INPUT_COLOR_MODE;\r
+BYTE OutputColorDepth = INPUT_COLOR_DEPTH ;\r
+BYTE bOutputColorMode = OUTPUT_COLOR_MODE ;\r
+\r
+BYTE iVideoModeSelect=0 ;\r
+\r
+ULONG VideoPixelClock ;\r
+BYTE VIC ; // 480p60\r
+BYTE pixelrep ; // no pixelrepeating\r
+HDMI_Aspec aspec ;\r
+HDMI_Colorimetry Colorimetry ;\r
+\r
+ULONG ulAudioSampleFS = INPUT_SAMPLE_FREQ_HZ ;\r
+// BYTE bAudioSampleFreq = INPUT_SAMPLE_FREQ ;\r
+BYTE bOutputAudioChannel = OUTPUT_CHANNEL ;\r
+\r
+BOOL bHDMIMode;\r
+BYTE bAudioEnable ;\r
+BYTE HPDStatus = FALSE;\r
+BYTE HPDChangeStatus = FALSE;\r
+BYTE bOutputAudioType=CNOFIG_INPUT_AUDIO_TYPE;\r
+////////////////////////////////////////////////////////////////////////////////\r
+// Function Prototype.\r
+////////////////////////////////////////////////////////////////////////////////\r
+BYTE ParseEDID();\r
+static BOOL ParseCEAEDID(BYTE *pCEAEDID);\r
+void ConfigAVIInfoFrame(BYTE VIC, BYTE pixelrep);\r
+void ConfigAudioInfoFrm();\r
+void Config_GeneralPurpose_Infoframe(BYTE *p3DInfoFrame);\r
+void ConfigfHdmiVendorSpecificInfoFrame(BYTE _3D_Stru);\r
+void InitHDMITX_Variable();\r
+void HDMITX_ChangeDisplayOption(HDMI_Video_Type VideoMode, HDMI_OutputColorMode OutputColorMode);\r
+void HDMITX_SetOutput();\r
+int HDMITX_DevLoopProc();\r
+////////////////////////////////////////////////////////////////////////////////\r
+// Function Body.\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+void InitHDMITX_Variable()\r
+{\r
+ printk( "[%s]\n", __FUNCTION__);\r
+ HDMITX_InitTxDev(&InstanceData);\r
+ HPDStatus = FALSE;\r
+ HPDChangeStatus = FALSE;\r
+}\r
+\r
+BOOL AudioModeDetect(void)\r
+{\r
+ setHDMITX_AudioChannelEnable(bAudioEnable);\r
+ return TRUE;\r
+}\r
+\r
+void HDMITX_ChangeColorDepth(BYTE colorDepth)\r
+{\r
+#ifdef IT6615\r
+ HDMITX_DEBUG_PRINTF(("OHDMITX_ChangeColorDepth(%02X)\n",(int)colorDepth)) ;\r
+ OutputColorDepth = colorDepth ;\r
+#else\r
+ OutputColorDepth = 0 ;\r
+#endif\r
+}\r
+\r
+void HDMITX_SetOutput()\r
+{\r
+ VIDEOPCLKLEVEL level ;\r
+ unsigned long TMDSClock = VideoPixelClock*(pixelrep+1);\r
+ HDMITX_DisableAudioOutput();\r
+ HDMITX_EnableHDCP(FALSE);\r
+\r
+ if( TMDSClock>80000000L )\r
+ {\r
+ level = PCLK_HIGH ;\r
+ }\r
+ else if(TMDSClock>20000000L)\r
+ {\r
+ level = PCLK_MEDIUM ;\r
+ }\r
+ else\r
+ {\r
+ level = PCLK_LOW ;\r
+ }\r
+#ifdef IT6615\r
+ HDMITX_DEBUG_PRINTF(("OutputColorDepth = %02X\n",(int)OutputColorDepth)) ;\r
+ setHDMITX_ColorDepthPhase(OutputColorDepth,0);\r
+#endif\r
+\r
+ setHDMITX_VideoSignalType(InstanceData.bInputVideoSignalType);\r
+ #ifdef SUPPORT_SYNCEMBEDDED\r
+ if(InstanceData.bInputVideoSignalType & T_MODE_SYNCEMB)\r
+ {\r
+ setHDMITX_SyncEmbeddedByVIC(VIC,InstanceData.bInputVideoSignalType);\r
+ }\r
+ #endif\r
+\r
+ HDMITX_DEBUG_PRINTF(("level = %d, ,bInputColorMode=%x,bOutputColorMode=%x,bHDMIMode=%x\n",(int)level,(int)bInputColorMode,(int)bOutputColorMode ,(int)bHDMIMode)) ;\r
+ HDMITX_EnableVideoOutput(level,bInputColorMode,bOutputColorMode ,bHDMIMode);\r
+\r
+ if( bHDMIMode )\r
+ {\r
+ #ifdef OUTPUT_3D_MODE\r
+ ConfigfHdmiVendorSpecificInfoFrame(OUTPUT_3D_MODE);\r
+ #endif\r
+ //HDMITX_EnableHDCP(TRUE);\r
+ ConfigAVIInfoFrame(VIC, pixelrep);\r
+\r
+ HDMITX_SetAudioOutput();\r
+\r
+ // if( bAudioEnable )\r
+ // {\r
+ // ConfigAudioInfoFrm();\r
+ // #ifdef SUPPORT_HBR_AUDIO\r
+ // HDMITX_EnableAudioOutput(T_AUDIO_HBR, CONFIG_INPUT_AUDIO_SPDIF, 768000L,8,NULL,TMDSClock);\r
+ // #else\r
+ // // HDMITX_EnableAudioOutput(T_AUDIO_LPCM, FALSE, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,TMDSClock);\r
+ // HDMITX_EnableAudioOutput(CNOFIG_INPUT_AUDIO_TYPE, CONFIG_INPUT_AUDIO_SPDIF, ulAudioSampleFS,bOutputAudioChannel,NULL,TMDSClock);\r
+ // #endif\r
+ // }\r
+\r
+ }\r
+ else\r
+ {\r
+ HDMITX_EnableAVIInfoFrame(FALSE ,NULL);\r
+ HDMITX_EnableVSInfoFrame(FALSE,NULL);\r
+ }\r
+ setHDMITX_AVMute(FALSE);\r
+ bChangeMode = FALSE ;\r
+ DumpHDMITXReg() ;\r
+}\r
+\r
+void HDMITX_ChangeAudioOption(BYTE Option, BYTE channelNum, BYTE AudioFs)\r
+{\r
+\r
+ switch(Option )\r
+ {\r
+ case T_AUDIO_HBR :\r
+ bOutputAudioType = T_AUDIO_HBR ;\r
+ ulAudioSampleFS = 768000L ;\r
+ bOutputAudioChannel = 8 ;\r
+ return ;\r
+ case T_AUDIO_NLPCM :\r
+ bOutputAudioType = T_AUDIO_NLPCM ;\r
+ bOutputAudioChannel = 2 ;\r
+ break ;\r
+ default:\r
+ bOutputAudioType = T_AUDIO_LPCM ;\r
+ if( channelNum < 1 )\r
+ {\r
+ bOutputAudioChannel = 1 ;\r
+ }\r
+ else if( channelNum > 8 )\r
+ {\r
+ bOutputAudioChannel = 8 ;\r
+ }\r
+ else\r
+ {\r
+ bOutputAudioChannel = channelNum ;\r
+ }\r
+ break ;\r
+ }\r
+\r
+ switch(AudioFs)\r
+ {\r
+ case AUDFS_44p1KHz:\r
+ ulAudioSampleFS = 44100L ;\r
+ break ;\r
+ case AUDFS_88p2KHz:\r
+ ulAudioSampleFS = 88200L ;\r
+ break ;\r
+ case AUDFS_176p4KHz:\r
+ ulAudioSampleFS = 176400L ;\r
+ break ;\r
+\r
+ case AUDFS_48KHz:\r
+ ulAudioSampleFS = 48000L ;\r
+ break ;\r
+ case AUDFS_96KHz:\r
+ ulAudioSampleFS = 96000L ;\r
+ break ;\r
+ case AUDFS_192KHz:\r
+ ulAudioSampleFS = 192000L ;\r
+ break ;\r
+\r
+ case AUDFS_768KHz:\r
+ ulAudioSampleFS = 768000L ;\r
+ break ;\r
+\r
+ case AUDFS_32KHz:\r
+ ulAudioSampleFS = 32000L ;\r
+ break ;\r
+ default:\r
+ ulAudioSampleFS = 48000L ;\r
+ break ;\r
+ }\r
+ HDMITX_DEBUG_PRINTF(("HDMITX_ChangeAudioOption():bOutputAudioType = %02X, ulAudioSampleFS = %8ld, bOutputAudioChannel = %d\n",(int)bOutputAudioType,ulAudioSampleFS,(int)bOutputAudioChannel)) ;\r
+ bChangeAudio = TRUE ;\r
+}\r
+\r
+void HDMITX_SetAudioOutput()\r
+{\r
+ if( bAudioEnable )\r
+ {\r
+ ConfigAudioInfoFrm();\r
+ // HDMITX_EnableAudioOutput(T_AUDIO_LPCM, FALSE, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,TMDSClock);\r
+ HDMITX_EnableAudioOutput(\r
+ //CNOFIG_INPUT_AUDIO_TYPE,\r
+ bOutputAudioType,\r
+ CONFIG_INPUT_AUDIO_SPDIF,\r
+ ulAudioSampleFS,\r
+ bOutputAudioChannel,\r
+ NULL, // pointer to cahnnel status.\r
+ VideoPixelClock*(pixelrep+1));\r
+ // if you have channel status , set here.\r
+ // setHDMITX_ChStat(BYTE ucIEC60958ChStat[]);\r
+ bChangeAudio = FALSE ;\r
+ }\r
+}\r
+\r
+int HDMITX_DevLoopProc()\r
+{\r
+ static BYTE DevLoopCount = 0 ;\r
+ CheckHDMITX(&HPDStatus,&HPDChangeStatus);\r
+\r
+ if( HPDChangeStatus )\r
+ {\r
+ if( HPDStatus )\r
+ {\r
+ HDMITX_PowerOn();\r
+ ParseEDID();\r
+ bOutputColorMode = F_MODE_RGB444;\r
+\r
+ if( RxCapability.ValidHDMI )\r
+ {\r
+ bHDMIMode = TRUE ;\r
+\r
+ if(RxCapability.VideoMode & (1<<6))\r
+ {\r
+ bAudioEnable = TRUE ;\r
+ }\r
+ if( RxCapability.VideoMode & (1<<5))\r
+ {\r
+ bOutputColorMode &= ~F_MODE_CLRMOD_MASK ;\r
+ bOutputColorMode |= F_MODE_YUV444;\r
+ }\r
+ else if (RxCapability.VideoMode & (1<<4))\r
+ {\r
+ bOutputColorMode &= ~F_MODE_CLRMOD_MASK ;\r
+ bOutputColorMode |= F_MODE_YUV422 ;\r
+ }\r
+\r
+ #ifdef IT6615\r
+ if(RxCapability.dc.uc & (HDMI_DC_SUPPORT_36|HDMI_DC_SUPPORT_30))\r
+ {\r
+ setHDMITX_ColorDepthPhase(OutputColorDepth,0);\r
+ }\r
+ else\r
+ {\r
+ OutputColorDepth = B_TX_CD_NODEF;\r
+ }\r
+ #else\r
+ OutputColorDepth = B_TX_CD_NODEF;\r
+ #endif\r
+ }\r
+ else\r
+ {\r
+ bHDMIMode = FALSE ;\r
+ bAudioEnable = FALSE ;\r
+ OutputColorDepth = B_TX_CD_NODEF;\r
+ // HDMITX_DisableAudioOutput();\r
+ // HDMITX_DisableVideoOutput();\r
+ #ifdef SUPPORT_HDCP\r
+ HDMITX_EnableHDCP(FALSE);\r
+ #endif\r
+ }\r
+ HDMITX_DEBUG_PRINTF(("HPD change HDMITX_SetOutput();\n"));\r
+ //HDMITX_SetOutput();\r
+ bChangeMode=TRUE;\r
+ bChangeAudio = TRUE ;\r
+ }\r
+ else\r
+ {\r
+ // unplug mode, ...\r
+ HDMITX_DEBUG_PRINTF(("HPD OFF HDMITX_DisableVideoOutput()\n"));\r
+ HDMITX_DisableVideoOutput();\r
+ HDMITX_PowerDown();\r
+ bChangeAudio = FALSE ;\r
+ }\r
+ }\r
+ else // no stable but need to process mode change procedure\r
+ {\r
+ if( DevLoopCount >= 20 )\r
+ {\r
+ DevLoopCount = 0 ;\r
+ }\r
+\r
+ #ifdef HDMITX_AUTO_MONITOR_INPUT\r
+ if( DevLoopCount == 0 )\r
+ {\r
+ HDMITX_MonitorInputVideoChange();\r
+ HDMITX_MonitorInputAudioChange();\r
+ }\r
+ #endif\r
+\r
+ if(HPDStatus)\r
+ {\r
+ #ifdef HDMITX_AUTO_MONITOR_INPUT\r
+ if( bChangeMode && ( VIC > 0 ) )\r
+ #else\r
+ if( bChangeMode )\r
+ #endif\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("Mode change HDMITX_SetOutput();\n"));\r
+ HDMITX_SetOutput();\r
+ // HDMITX_EnableHDCP(TRUE);\r
+\r
+ bChangeMode = FALSE ;\r
+ }\r
+ if(getHDMITX_LinkStatus())\r
+ {\r
+ // AudioModeDetect();\r
+ #ifdef SUPPORT_HDCP\r
+ if(getHDMITX_AuthenticationDone() ==FALSE)\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("getHDMITX_AuthenticationDone() ==FALSE\n") );\r
+ HDMITX_EnableHDCP(TRUE);\r
+ setHDMITX_AVMute(FALSE);\r
+ }\r
+ #endif\r
+ }\r
+\r
+ if(bChangeAudio)\r
+ {\r
+ HDMITX_SetAudioOutput() ;\r
+ }\r
+ }\r
+ }\r
+\r
+ DevLoopCount ++ ;\r
+ return HPDStatus;\r
+}\r
+\r
+#ifdef HDMITX_AUTO_MONITOR_INPUT\r
+\r
+void HDMITX_MonitorInputAudioChange()\r
+{\r
+ static ULONG prevAudioSampleFS = 0 ;\r
+ LONG AudioFS ;\r
+\r
+ if( !bAudioEnable )\r
+ {\r
+ prevAudioSampleFS = 0 ;\r
+ }\r
+ else\r
+ {\r
+ AudioFS = CalcAudFS() ;\r
+ HDMITX_DEBUG_PRINTF1(("Audio Chagne, Audio clock = %ldHz\n",AudioFS)) ;\r
+ if( AudioFS > 188000L ) // 192KHz\r
+ {\r
+ ulAudioSampleFS = 192000L ;\r
+ }\r
+ else if( AudioFS > 144000L ) // 176.4KHz\r
+ {\r
+ ulAudioSampleFS = 176400L ;\r
+ }\r
+ else if( AudioFS > 93000L ) // 96KHz\r
+ {\r
+ ulAudioSampleFS = 96000L ;\r
+ }\r
+ else if( AudioFS > 80000L ) // 88.2KHz\r
+ {\r
+ ulAudioSampleFS = 88200L ;\r
+ }\r
+ else if( AudioFS > 45000L ) // 48 KHz\r
+ {\r
+ ulAudioSampleFS = 48000L ;\r
+ }\r
+ else if( AudioFS > 36000L ) // 44.1KHz\r
+ {\r
+ ulAudioSampleFS = 44100L ;\r
+ }\r
+ else // 32KHz\r
+ {\r
+ ulAudioSampleFS = 32000L ;\r
+ }\r
+\r
+ if(!bChangeMode)\r
+ {\r
+ if( ulAudioSampleFS != prevAudioSampleFS )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("ulAudioSampleFS = %ldHz -> %ldHz\n",ulAudioSampleFS,ulAudioSampleFS)) ;\r
+ ConfigAudioInfoFrm();\r
+ HDMITX_EnableAudioOutput(CNOFIG_INPUT_AUDIO_TYPE, CONFIG_INPUT_AUDIO_SPDIF, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,0);\r
+ // HDMITX_EnableAudioOutput(T_AUDIO_LPCM, FALSE, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,0);\r
+\r
+ }\r
+ }\r
+\r
+ prevAudioSampleFS = ulAudioSampleFS ;\r
+\r
+ }\r
+}\r
+\r
+int HDMITX_SearchVICIndex( ULONG PCLK, USHORT HTotal, USHORT VTotal, BYTE ScanMode )\r
+{\r
+ #define SEARCH_COUNT 4\r
+ unsigned long pclkDiff;\r
+ int i;\r
+ char hit;\r
+ int iMax[SEARCH_COUNT]={0};\r
+ char hitMax[SEARCH_COUNT]={0};\r
+ char i2;\r
+\r
+ for( i = 0 ; i < SizeofVMTable; i++ )\r
+ {\r
+ if( s_VMTable[i].VIC == 0 ) break ;\r
+\r
+ hit=0;\r
+\r
+ if( ScanMode == s_VMTable[i].ScanMode )\r
+ {\r
+ hit++;\r
+\r
+ if( ScanMode == INTERLACE )\r
+ {\r
+ if( DIFF(VTotal/2, s_VMTable[i].VTotal) < 10 )\r
+ {\r
+ hit++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( DIFF(VTotal, s_VMTable[i].VTotal) < 10 )\r
+ {\r
+ hit++;\r
+ }\r
+ }\r
+\r
+ if( hit == 2 ) // match scan mode and v-total\r
+ {\r
+ if( DIFF(HTotal, s_VMTable[i].HTotal) < 40 )\r
+ {\r
+ hit++;\r
+\r
+ pclkDiff = DIFF(PCLK, s_VMTable[i].PCLK);\r
+ pclkDiff = (pclkDiff * 100) / s_VMTable[i].PCLK;\r
+\r
+ if( pclkDiff < 100 )\r
+ {\r
+ hit += ( 100 - pclkDiff );\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ HDMITX_DEBUG_PRINTF(("i = %d, hit = %d\n",i,(int)hit));\r
+\r
+ if( hit )\r
+ {\r
+ for( i2=0 ; i2<SEARCH_COUNT ; i2++ )\r
+ {\r
+ if( hitMax[i2] < hit )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("replace iMax[%d] = %d => %d\n",(int)i2, iMax[i2], i ));\r
+ hitMax[i2] = hit;\r
+ iMax[i2]=i;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ i=-1;\r
+ hit=0;\r
+ for( i2=0 ; i2<SEARCH_COUNT ; i2++ )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("[%d] i = %d, hit = %d\n",(int)i2, iMax[i2],(int)hitMax[i2]));\r
+ if( hitMax[i2] > hit )\r
+ {\r
+ hit = hitMax[i2];\r
+ i = iMax[i2];\r
+ }\r
+ }\r
+\r
+ if( hit > 2 )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("i = %d, hit = %d\n",i,(int)hit));\r
+ HDMITX_DEBUG_PRINTF((">> mode : %d %u x %u @%lu (%s)\n", (int)s_VMTable[i].VIC, s_VMTable[i].HActive, s_VMTable[i].VActive, s_VMTable[i].PCLK, (s_VMTable[i].ScanMode==0)?"i":"p" ));\r
+ }\r
+ else\r
+ {\r
+ i=-1;\r
+ HDMITX_DEBUG_PRINTF(("no matched\n"));\r
+ }\r
+\r
+ return i;\r
+}\r
+\r
+void HDMITX_MonitorInputVideoChange()\r
+{\r
+ static ULONG prevPCLK = 0 ;\r
+ static USHORT prevHTotal = 0 ;\r
+ static USHORT prevVTotal = 0 ;\r
+ static BYTE prevScanMode ;\r
+ ULONG currPCLK ;\r
+ ULONG diff ;\r
+ USHORT currHTotal, currVTotal ;\r
+ BYTE currScanMode ;\r
+ int i ;\r
+\r
+ currPCLK = CalcPCLK() ;\r
+ currHTotal = hdmitx_getInputHTotal() ;\r
+ currVTotal = hdmitx_getInputVTotal() ;\r
+ currScanMode = hdmitx_isInputInterlace() ? INTERLACE:PROG ;\r
+ diff = DIFF(currPCLK,prevPCLK);\r
+\r
+ HDMITX_DEBUG_PRINTF(("HDMITX_MonitorInputVideoChange : pclk=%lu, ht=%u, vt=%u, dif=%lu\n", currPCLK, currHTotal, currVTotal, diff ));\r
+\r
+ if( currHTotal == 0 || currVTotal == 0 || currPCLK == 0 )\r
+ {\r
+ bChangeMode = FALSE;\r
+ return ;\r
+ }\r
+\r
+ if( diff > currPCLK/20) // 5% torrenlance\r
+ {\r
+ bChangeMode = TRUE ;\r
+ }\r
+ else\r
+ {\r
+ diff = DIFF(currHTotal, prevHTotal) ;\r
+ if( diff > 20 )\r
+ {\r
+ bChangeMode = TRUE ;\r
+ }\r
+ diff = DIFF(currVTotal, prevVTotal) ;\r
+ if( diff > 20 )\r
+ {\r
+ bChangeMode = TRUE ;\r
+ }\r
+ }\r
+\r
+ if( bChangeMode )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("PCLK = %ld -> %ld\n",prevPCLK, currPCLK));\r
+ HDMITX_DEBUG_PRINTF(("HTotal = %d -> %d\n",prevHTotal, currHTotal));\r
+ HDMITX_DEBUG_PRINTF(("VTotal = %d -> %d\n",prevVTotal, currVTotal));\r
+ HDMITX_DEBUG_PRINTF(("ScanMode = %s -> %s\n",prevScanMode?"P":"I", currScanMode?"P":"I"));\r
+\r
+ HDMITX_DEBUG_PRINTF(("PCLK = %ld,(%dx%d) %s %s\n",currPCLK, currHTotal,currVTotal, (currScanMode==INTERLACE)?"INTERLACED":"PROGRESS",bChangeMode?"CHANGE MODE":"NO CHANGE MODE"));\r
+\r
+ setHDMITX_AVMute(TRUE);\r
+\r
+ #if 0\r
+ for( i = 0 ; (i < SizeofVMTable) && ( s_VMTable[i].VIC != 0 ); i++ )\r
+ {\r
+ if( s_VMTable[i].VIC == 0 ) break ;\r
+ if( DIFF(currPCLK, s_VMTable[i].PCLK) > (s_VMTable[i].PCLK/20))\r
+ {\r
+ continue ;\r
+ }\r
+ if( DIFF(currHTotal, s_VMTable[i].HTotal) > 40 )\r
+ {\r
+ continue ;\r
+ }\r
+ if( currScanMode != s_VMTable[i].ScanMode )\r
+ {\r
+ continue ;\r
+ }\r
+ if( currScanMode == INTERLACE )\r
+ {\r
+ if( DIFF(currVTotal/2, s_VMTable[i].VTotal) > 10 )\r
+ {\r
+ continue ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( DIFF(currVTotal, s_VMTable[i].VTotal) > 10 )\r
+ {\r
+ continue ;\r
+ }\r
+ }\r
+ printf("i = %d, VIC = %d\n",i,(int)s_VMTable[i].VIC) ;\r
+\r
+ break ;\r
+ }\r
+ #else\r
+ i = HDMITX_SearchVICIndex( currPCLK, currHTotal, currVTotal, currScanMode );\r
+ #endif\r
+\r
+ if( i >= 0 )\r
+ {\r
+ VIC = s_VMTable[i].VIC;\r
+ pixelrep = s_VMTable[i].PixelRep ;\r
+ VideoPixelClock = currPCLK ;\r
+ }\r
+ else\r
+ {\r
+ VIC = 0;\r
+ pixelrep = 0;\r
+ VideoPixelClock = 0 ;\r
+ }\r
+ }\r
+\r
+ prevPCLK = currPCLK ;\r
+ prevHTotal = currHTotal ;\r
+ prevVTotal = currVTotal ;\r
+ prevScanMode = currScanMode ;\r
+\r
+}\r
+#endif // HDMITX_AUTO_MONITOR_INPUT\r
+\r
+void HDMITX_ChangeDisplayOption(HDMI_Video_Type OutputVideoTiming, HDMI_OutputColorMode OutputColorMode)\r
+{\r
+ printk( "[%s] Vic=%d\n", __FUNCTION__,OutputVideoTiming);\r
+ //HDMI_Video_Type t=HDMI_480i60_16x9;\r
+ if((F_MODE_RGB444)==(bOutputColorMode&F_MODE_CLRMOD_MASK))//Force output RGB in RGB only case\r
+ {\r
+ OutputColorMode=F_MODE_RGB444;\r
+ }\r
+ else if ((F_MODE_YUV422)==(bOutputColorMode&F_MODE_CLRMOD_MASK))//YUV422 only\r
+ {\r
+ if(OutputColorMode==HDMI_YUV444){OutputColorMode=F_MODE_YUV422;}\r
+ }\r
+ else if ((F_MODE_YUV444)==(bOutputColorMode&F_MODE_CLRMOD_MASK))//YUV444 only\r
+ {\r
+ if(OutputColorMode==HDMI_YUV422){OutputColorMode=F_MODE_YUV444;}\r
+ }\r
+ switch(OutputVideoTiming)\r
+ {\r
+ case HDMI_640x480p60:\r
+ VIC = 1 ;\r
+ VideoPixelClock = 25000000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_4x3 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_480p60:\r
+ VIC = 2 ;\r
+ VideoPixelClock = 27000000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_4x3 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_480p60_16x9:\r
+ VIC = 3 ;\r
+ VideoPixelClock = 27000000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_720p60:\r
+ VIC = 4 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_1080i60:\r
+ VIC = 5 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_480i60:\r
+ VIC = 6 ;\r
+ VideoPixelClock = 13500000 ;\r
+ pixelrep = 1 ;\r
+ aspec = HDMI_4x3 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_480i60_16x9:\r
+ VIC = 7 ;\r
+ VideoPixelClock = 13500000 ;\r
+ pixelrep = 1 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_1080p60:\r
+ VIC = 16 ;\r
+ VideoPixelClock = 148500000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_576p50:\r
+ VIC = 17 ;\r
+ VideoPixelClock = 27000000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_4x3 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_576p50_16x9:\r
+ VIC = 18 ;\r
+ VideoPixelClock = 27000000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_720p50:\r
+ VIC = 19 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_1080i50:\r
+ VIC = 20 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_576i50:\r
+ VIC = 21 ;\r
+ VideoPixelClock = 13500000 ;\r
+ pixelrep = 1 ;\r
+ aspec = HDMI_4x3 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_576i50_16x9:\r
+ VIC = 22 ;\r
+ VideoPixelClock = 13500000 ;\r
+ pixelrep = 1 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU601 ;\r
+ break ;\r
+ case HDMI_1080p50:\r
+ VIC = 31 ;\r
+ VideoPixelClock = 148500000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_1080p24:\r
+ VIC = 32 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_1080p25:\r
+ VIC = 33 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+ case HDMI_1080p30:\r
+ VIC = 34 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+ break ;\r
+\r
+ case HDMI_720p30:\r
+ VIC = 0 ;\r
+ VideoPixelClock = 74250000 ;\r
+ pixelrep = 0 ;\r
+ aspec = HDMI_16x9 ;\r
+ Colorimetry = HDMI_ITU709 ;\r
+\r
+ #ifdef SUPPORT_SYNCEMBEDDED\r
+ /*\r
+ VTiming.HActive=1280 ;\r
+ VTiming.VActive=720 ;\r
+ VTiming.HTotal=3300 ;\r
+ VTiming.VTotal=750 ;\r
+ VTiming.PCLK=VideoPixelClock ;\r
+ VTiming.xCnt=0x2E ;\r
+ VTiming.HFrontPorch= 1760;\r
+ VTiming.HSyncWidth= 40 ;\r
+ VTiming.HBackPorch= 220 ;\r
+ VTiming.VFrontPorch= 5;\r
+ VTiming.VSyncWidth= 5 ;\r
+ VTiming.VBackPorch= 20 ;\r
+ VTiming.ScanMode=PROG ;\r
+ VTiming.VPolarity=Vneg ;\r
+ VTiming.HPolarity=Hneg ;\r
+ */\r
+ #endif\r
+ break ;\r
+ default:\r
+ bChangeMode = FALSE ;\r
+ return ;\r
+ }\r
+ switch(OutputColorMode)\r
+ {\r
+ case HDMI_YUV444:\r
+ bOutputColorMode = F_MODE_YUV444 ;\r
+ break ;\r
+ case HDMI_YUV422:\r
+ bOutputColorMode = F_MODE_YUV422 ;\r
+ break ;\r
+ case HDMI_RGB444:\r
+ default:\r
+ bOutputColorMode = F_MODE_RGB444 ;\r
+ break ;\r
+ }\r
+ if( Colorimetry == HDMI_ITU709 )\r
+ {\r
+ bInputColorMode |= F_VIDMODE_ITU709 ;\r
+ }\r
+ else\r
+ {\r
+ bInputColorMode &= ~F_VIDMODE_ITU709 ;\r
+ }\r
+ // if( Colorimetry != HDMI_640x480p60)\r
+ if( OutputVideoTiming != HDMI_640x480p60)\r
+ {\r
+ bInputColorMode |= F_VIDMODE_16_235 ;\r
+ }\r
+ else\r
+ {\r
+ bInputColorMode &= ~F_VIDMODE_16_235 ;\r
+ }\r
+ bChangeMode = TRUE ;\r
+}\r
+\r
+void ConfigAVIInfoFrame(BYTE VIC, BYTE pixelrep)\r
+{\r
+ AVI_InfoFrame *AviInfo;\r
+ AviInfo = (AVI_InfoFrame *)CommunBuff ;\r
+\r
+ AviInfo->pktbyte.AVI_HB[0] = AVI_INFOFRAME_TYPE|0x80 ;\r
+ AviInfo->pktbyte.AVI_HB[1] = AVI_INFOFRAME_VER ;\r
+ AviInfo->pktbyte.AVI_HB[2] = AVI_INFOFRAME_LEN ;\r
+\r
+ switch(bOutputColorMode)\r
+ {\r
+ case F_MODE_YUV444:\r
+ // AviInfo->info.ColorMode = 2 ;\r
+ AviInfo->pktbyte.AVI_DB[0] = (2<<5)|(1<<4);\r
+ break ;\r
+ case F_MODE_YUV422:\r
+ // AviInfo->info.ColorMode = 1 ;\r
+ AviInfo->pktbyte.AVI_DB[0] = (1<<5)|(1<<4);\r
+ break ;\r
+ case F_MODE_RGB444:\r
+ default:\r
+ // AviInfo->info.ColorMode = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[0] = (0<<5)|(1<<4);\r
+ break ;\r
+ }\r
+ AviInfo->pktbyte.AVI_DB[1] = 8 ;\r
+ AviInfo->pktbyte.AVI_DB[1] |= (aspec != HDMI_16x9)?(1<<4):(2<<4); // 4:3 or 16:9\r
+ AviInfo->pktbyte.AVI_DB[1] |= (Colorimetry != HDMI_ITU709)?(1<<6):(2<<6); // 4:3 or 16:9\r
+ AviInfo->pktbyte.AVI_DB[2] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[3] = VIC ;\r
+ AviInfo->pktbyte.AVI_DB[4] = pixelrep & 3 ;\r
+ AviInfo->pktbyte.AVI_DB[5] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[6] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[7] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[8] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[9] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[10] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[11] = 0 ;\r
+ AviInfo->pktbyte.AVI_DB[12] = 0 ;\r
+\r
+ HDMITX_EnableAVIInfoFrame(TRUE, (unsigned char *)AviInfo);\r
+}\r
+\r
+////////////////////////////////////////////////////////////////////////////////\r
+// Function: ConfigAudioInfoFrm\r
+// Parameter: NumChannel, number from 1 to 8\r
+// Return: ER_SUCCESS for successfull.\r
+// Remark: Evaluate. The speakerplacement is only for reference.\r
+// For production, the caller of hdmitx_SetAudioInfoFrame should program\r
+// Speaker placement by actual status.\r
+// Side-Effect:\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+void ConfigAudioInfoFrm()\r
+{\r
+ int i ;\r
+\r
+ Audio_InfoFrame *AudioInfo ;\r
+ AudioInfo = (Audio_InfoFrame *)CommunBuff ;\r
+\r
+ HDMITX_DEBUG_PRINTF(("ConfigAudioInfoFrm(%d)\n",2));\r
+\r
+ AudioInfo->pktbyte.AUD_HB[0] = AUDIO_INFOFRAME_TYPE ;\r
+ AudioInfo->pktbyte.AUD_HB[1] = 1 ;\r
+ AudioInfo->pktbyte.AUD_HB[2] = AUDIO_INFOFRAME_LEN ;\r
+ AudioInfo->pktbyte.AUD_DB[0] = 1 ;\r
+ for( i = 1 ;i < AUDIO_INFOFRAME_LEN ; i++ )\r
+ {\r
+ AudioInfo->pktbyte.AUD_DB[i] = 0 ;\r
+ }\r
+ HDMITX_EnableAudioInfoFrame(TRUE, (unsigned char *)AudioInfo);\r
+}\r
+\r
+void ConfigfHdmiVendorSpecificInfoFrame(BYTE _3D_Stru)\r
+{\r
+ VendorSpecific_InfoFrame *VS_Info;\r
+\r
+ VS_Info=(VendorSpecific_InfoFrame *)CommunBuff ;\r
+\r
+ VS_Info->pktbyte.VS_HB[0] = VENDORSPEC_INFOFRAME_TYPE|0x80;\r
+ VS_Info->pktbyte.VS_HB[1] = VENDORSPEC_INFOFRAME_VER;\r
+ VS_Info->pktbyte.VS_HB[2] = (_3D_Stru == Side_by_Side)?6:5;\r
+ VS_Info->pktbyte.VS_DB[0] = 0x03;\r
+ VS_Info->pktbyte.VS_DB[1] = 0x0C;\r
+ VS_Info->pktbyte.VS_DB[2] = 0x00;\r
+ VS_Info->pktbyte.VS_DB[3] = 0x40;\r
+ switch(_3D_Stru)\r
+ {\r
+ case Side_by_Side:\r
+ case Frame_Pcaking:\r
+ case Top_and_Botton:\r
+ VS_Info->pktbyte.VS_DB[4] = (_3D_Stru<<4);\r
+ break;\r
+ default:\r
+ VS_Info->pktbyte.VS_DB[4] = (Frame_Pcaking<<4);\r
+ break ;\r
+ }\r
+ VS_Info->pktbyte.VS_DB[5] = 0x00;\r
+ HDMITX_EnableVSInfoFrame(TRUE,(BYTE *)VS_Info);\r
+}\r
+\r
+/////////////////////////////////////////////////////////////////////\r
+// ParseEDID()\r
+// Check EDID check sum and EDID 1.3 extended segment.\r
+/////////////////////////////////////////////////////////////////////\r
+\r
+BYTE ParseEDID()\r
+{\r
+ // collect the EDID ucdata of segment 0\r
+ _XDATA unsigned char *EDID_Buf;\r
+ BYTE CheckSum ;\r
+ BYTE BlockCount ;\r
+ BYTE err ;\r
+ BYTE bValidCEA = FALSE ;\r
+ BYTE i;\r
+ #if Debug_message\r
+ BYTE j ;\r
+ #endif // Debug_message\r
+\r
+ EDID_Buf = CommunBuff;\r
+ RxCapability.ValidCEA = FALSE ;\r
+ RxCapability.ValidHDMI = FALSE ;\r
+ RxCapability.dc.uc = 0;\r
+\r
+ getHDMITX_EDIDBlock(0, EDID_Buf);\r
+\r
+ for( i = 0, CheckSum = 0 ; i < 128 ; i++ )\r
+ {\r
+ CheckSum += EDID_Buf[i] ; CheckSum &= 0xFF ;\r
+ }\r
+ //Eep_Write(0x80, 0x80, EDID_Buf);\r
+ if( CheckSum != 0 )\r
+ {\r
+ return FALSE ;\r
+ }\r
+ if( EDID_Buf[0] != 0x00 ||\r
+ EDID_Buf[1] != 0xFF ||\r
+ EDID_Buf[2] != 0xFF ||\r
+ EDID_Buf[3] != 0xFF ||\r
+ EDID_Buf[4] != 0xFF ||\r
+ EDID_Buf[5] != 0xFF ||\r
+ EDID_Buf[6] != 0xFF ||\r
+ EDID_Buf[7] != 0x00)\r
+ {\r
+ return FALSE ;\r
+ }\r
+ /*\r
+ for( i = 0 ; i < 128 ; i++ )\r
+ {\r
+ HDMITX_DEBUG_PRINTF(("%02X%c",(int)EDID_Buf[i],(7 == (i&7))?'\n':' '));\r
+ }\r
+ */\r
+\r
+ BlockCount = EDID_Buf[0x7E] ;\r
+\r
+ if( BlockCount == 0 )\r
+ {\r
+ return TRUE ; // do nothing.\r
+ }\r
+ else if ( BlockCount > 4 )\r
+ {\r
+ BlockCount = 4 ;\r
+ }\r
+ // read all segment for test\r
+ for( i = 1 ; i <= BlockCount ; i++ )\r
+ {\r
+ err = getHDMITX_EDIDBlock(i, EDID_Buf);\r
+\r
+ #if Debug_message\r
+ for( j = 0 ; j < 128 ; j++ )\r
+ {\r
+ EDID_DEBUG_PRINTF(("%02X%c",(int)EDID_Buf[j],(7 == (j&7))?'\n':' '));\r
+ }\r
+ #endif // Debug_message\r
+\r
+ if( err )\r
+ {\r
+ if( !bValidCEA && EDID_Buf[0] == 0x2 && EDID_Buf[1] == 0x3 )\r
+ {\r
+ err = ParseCEAEDID(EDID_Buf);\r
+ EDID_DEBUG_PRINTF(("err = %s\n",err?"SUCCESS":"FAIL"));\r
+ if( err )\r
+ {\r
+ EDID_DEBUG_PRINTF(("RxCapability.IEEEOUI = %lx\n",RxCapability.IEEEOUI));\r
+\r
+ if(RxCapability.IEEEOUI==0x0c03)\r
+ {\r
+ RxCapability.ValidHDMI = TRUE ;\r
+ bValidCEA = TRUE ;\r
+ }\r
+ else\r
+ {\r
+ RxCapability.ValidHDMI = FALSE ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return err ;\r
+}\r
+\r
+static BOOL ParseCEAEDID(BYTE *pCEAEDID)\r
+{\r
+ BYTE offset,End ;\r
+ BYTE count ;\r
+ BYTE tag ;\r
+ int i ;\r
+\r
+ if( pCEAEDID[0] != 0x02 || pCEAEDID[1] != 0x03 ) return FALSE ; // not a CEA BLOCK.\r
+ End = pCEAEDID[2] ; // CEA description.\r
+\r
+ RxCapability.VDOMode[0] = 0x00 ;\r
+ RxCapability.VDOMode[1] = 0x00 ;\r
+ RxCapability.VDOMode[2] = 0x00 ;\r
+ RxCapability.VDOMode[3] = 0x00 ;\r
+ RxCapability.VDOMode[4] = 0x00 ;\r
+ RxCapability.VDOMode[5] = 0x00 ;\r
+ RxCapability.VDOMode[6] = 0x00 ;\r
+ RxCapability.VDOMode[7] = 0x00 ;\r
+ RxCapability.PA[0] = 0x00 ;\r
+ RxCapability.PA[1] = 0x00 ;\r
+\r
+ RxCapability.VideoMode = pCEAEDID[3] ;\r
+\r
+ RxCapability.NativeVDOMode = 0xff ;\r
+\r
+ for( offset = 4 ; offset < End ; )\r
+ {\r
+ tag = pCEAEDID[offset] >> 5 ;\r
+ count = pCEAEDID[offset] & 0x1f ;\r
+ switch( tag )\r
+ {\r
+ case 0x01: // Audio Data Block ;\r
+ RxCapability.AUDDesCount = count/3 ;\r
+ EDID_DEBUG_PRINTF(("RxCapability.AUDDesCount = %d\n",(int)RxCapability.AUDDesCount));\r
+ offset++ ;\r
+ for( i = 0 ; i < RxCapability.AUDDesCount && i < MAX_AUDDES_COUNT ; i++ )\r
+ {\r
+ RxCapability.AUDDes[i].uc[0] = pCEAEDID[offset+i*3] ;\r
+ RxCapability.AUDDes[i].uc[1] = pCEAEDID[offset+i*3+1] ;\r
+ RxCapability.AUDDes[i].uc[2] = pCEAEDID[offset+i*3+2] ;\r
+ }\r
+ offset += count ;\r
+ break ;\r
+\r
+ case 0x02: // Video Data Block ;\r
+ offset ++ ;\r
+ for( i = 0,RxCapability.NativeVDOMode = 0xff ; i < count ; i++)\r
+ {\r
+ BYTE VIC ;\r
+ VIC = pCEAEDID[offset+i] & (~0x80);\r
+ // if( FindModeTableEntryByVIC(VIC) != -1 )\r
+ if(VIC<64)\r
+ {\r
+ RxCapability.VDOMode[VIC/8] |= (1<<(VIC%8));\r
+ EDID_DEBUG_PRINTF(("VIC = %d, RxCapability.VDOMode[%d]=%02X\n",(int)VIC,(int)VIC/8,(int)RxCapability.VDOMode[VIC/8] ));\r
+ if(( pCEAEDID[offset+i] & 0x80 )&&(RxCapability.NativeVDOMode==0xFF))\r
+ {\r
+ RxCapability.NativeVDOMode = VIC ;\r
+ EDID_DEBUG_PRINTF(("native = %d\n",RxCapability.NativeVDOMode));\r
+ }\r
+ }\r
+ }\r
+ offset += count ;\r
+ break ;\r
+\r
+ case 0x03: // Vendor Specific Data Block ;\r
+ offset ++ ;\r
+ RxCapability.IEEEOUI = (ULONG)pCEAEDID[offset+2] ;\r
+ RxCapability.IEEEOUI <<= 8 ;\r
+ RxCapability.IEEEOUI += (ULONG)pCEAEDID[offset+1] ;\r
+ RxCapability.IEEEOUI <<= 8 ;\r
+ RxCapability.IEEEOUI += (ULONG)pCEAEDID[offset] ;\r
+ EDID_DEBUG_PRINTF(("IEEEOUI = %02X %02X %02X %lx",(int)pCEAEDID[offset+2],(int)pCEAEDID[offset+1],(int)pCEAEDID[offset],RxCapability.IEEEOUI));\r
+ if( RxCapability.IEEEOUI== 0x0C03)\r
+ {\r
+ BYTE nextoffset ;\r
+ RxCapability.PA[0] = pCEAEDID[offset+3] ;\r
+ RxCapability.PA[1] = pCEAEDID[offset+4] ;\r
+ if(count>5)\r
+ {\r
+ RxCapability.dc.uc = pCEAEDID[offset+5]&0x70;\r
+ }\r
+ if(count>6)\r
+ {\r
+ RxCapability.MaxTMDSClock = pCEAEDID[offset+6];\r
+ }\r
+ if(count>7)\r
+ {\r
+ nextoffset = 8 ;\r
+ if(pCEAEDID[offset+7] & 0x80) { nextoffset += 2 ; } // latency\r
+ if(pCEAEDID[offset+7] & 0x40) { nextoffset += 2 ; } // interlace latency\r
+ if(pCEAEDID[offset+7] & 0x20) {\r
+ EDID_DEBUG_PRINTF(("next offset = %d",(int)nextoffset));\r
+ RxCapability.Valid3D = (pCEAEDID[offset+nextoffset] & 0x80)?TRUE:FALSE ;\r
+ } // interlace latency\r
+\r
+ }\r
+ }\r
+ offset += count ; // ignore the remaind.\r
+\r
+ break ;\r
+\r
+ case 0x04: // Speaker Data Block ;\r
+ offset ++ ;\r
+ RxCapability.SpeakerAllocBlk.uc[0] = pCEAEDID[offset] ;\r
+ RxCapability.SpeakerAllocBlk.uc[1] = pCEAEDID[offset+1] ;\r
+ RxCapability.SpeakerAllocBlk.uc[2] = pCEAEDID[offset+2] ;\r
+ offset += 3 ;\r
+ break ;\r
+ case 0x05: // VESA Data Block ;\r
+ offset += count+1 ;\r
+ break ;\r
+ case 0x07: // Extended Data Block ;\r
+ offset += count+1 ; //ignore\r
+ break ;\r
+ default:\r
+ offset += count+1 ; // ignore\r
+ }\r
+ }\r
+ RxCapability.ValidCEA = TRUE ;\r
+ return TRUE ;\r
+}\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <hdmitx_sys.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+#ifndef _HDMITX_SYS_H_\r
+#define _HDMITX_SYS_H_\r
+#include "cat66121_hdmi_hw.h"\r
+#endif // _HDMITX_SYS_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <sha1.c>\r
+// @author Hermes.Wu@ite.com.tw\r
+// @date 2011/08/26\r
+// @fileversion: COMMON_FILE_1.01\r
+//******************************************/\r
+\r
+#include <stdio.h>\r
+//#include <stdlib.h>\r
+#include "sha1.h"\r
+\r
+\r
+#ifndef DISABLE_HDCP\r
+\r
+#define WCOUNT 17\r
+ULONG VH[5];\r
+ULONG w[WCOUNT];\r
+\r
+#define rol(x,y)(((x)<< (y))| (((ULONG)x)>> (32-y)))\r
+\r
+\r
+void SHATransform(ULONG * h)\r
+{\r
+ int t;\r
+ ULONG tmp;\r
+\r
+\r
+ h[0]=0x67452301;\r
+ h[1]=0xefcdab89;\r
+ h[2]=0x98badcfe;\r
+ h[3]=0x10325476;\r
+ h[4]=0xc3d2e1f0;\r
+\r
+ for (t=0; t < 20; t++){\r
+ if(t>=16)\r
+ {\r
+ tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];\r
+ w[(t)% WCOUNT]=rol(tmp,1);\r
+ }\r
+ HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));\r
+\r
+ tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[3] & ~h[1]))+ h[4] + w[(t)% WCOUNT] + 0x5a827999;\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+\r
+ h[4]=h[3];\r
+ h[3]=h[2];\r
+ h[2]=rol(h[1],30);\r
+ h[1]=h[0];\r
+ h[0]=tmp;\r
+\r
+ }\r
+ for (t=20; t < 40; t++){\r
+ tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];\r
+ w[(t)% WCOUNT]=rol(tmp,1);\r
+ HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));\r
+ tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0x6ed9eba1;\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+ h[4]=h[3];\r
+ h[3]=h[2];\r
+ h[2]=rol(h[1],30);\r
+ h[1]=h[0];\r
+ h[0]=tmp;\r
+ }\r
+ for (t=40; t < 60; t++){\r
+ tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];\r
+ w[(t)% WCOUNT]=rol(tmp,1);\r
+ HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));\r
+ tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[1] & h[3])| (h[2] & h[3]))+ h[4] + w[(t)% WCOUNT] + 0x8f1bbcdc;\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+ h[4]=h[3];\r
+ h[3]=h[2];\r
+ h[2]=rol(h[1],30);\r
+ h[1]=h[0];\r
+ h[0]=tmp;\r
+ }\r
+ for (t=60; t < 80; t++)\r
+ {\r
+ tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];\r
+ w[(t)% WCOUNT]=rol(tmp,1);\r
+ HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));\r
+ tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0xca62c1d6;\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+ h[4]=h[3];\r
+ h[3]=h[2];\r
+ h[2]=rol(h[1],30);\r
+ h[1]=h[0];\r
+ h[0]=tmp;\r
+ }\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+ h[0] +=0x67452301;\r
+ h[1] +=0xefcdab89;\r
+ h[2] +=0x98badcfe;\r
+ h[3] +=0x10325476;\r
+ h[4] +=0xc3d2e1f0;\r
+\r
+ HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));\r
+}\r
+\r
+void SHA_Simple(void *p,WORD len,BYTE *output)\r
+{\r
+ // SHA_State s;\r
+ WORD i,t;\r
+ ULONG c;\r
+ BYTE *pBuff=p;\r
+\r
+ for(i=0;i < len;i++)\r
+ {\r
+ t=i/4;\r
+ if(i%4==0)\r
+ {\r
+ w[t]=0;\r
+ }\r
+ c=pBuff[i];\r
+ c <<=(3-(i%4))*8;\r
+ w[t] |=c;\r
+ HDCP_DEBUG_PRINTF2(("pBuff[%d]=%02X,c=%08lX,w[%d]=%08lX\n",(int)i,(int)pBuff[i],c,(int)t,w[t]));\r
+ }\r
+ t=i/4;\r
+ if(i%4==0)\r
+ {\r
+ w[t]=0;\r
+ }\r
+ //c=0x80 << ((3-i%4)*24);\r
+ c=0x80;\r
+ c <<=((3-i%4)*8);\r
+ w[t]|=c;t++;\r
+ for(; t < 15;t++)\r
+ {\r
+ w[t]=0;\r
+ }\r
+ w[15]=len*8;\r
+\r
+ for(i = 0 ; i < 16 ; i++)\r
+ {\r
+ HDCP_DEBUG_PRINTF2(("w[%d] = %08lX\n",i,w[i]));\r
+ }\r
+\r
+ SHATransform(VH);\r
+\r
+ for(i=0;i < 5;i++)\r
+ {\r
+ output[i*4+3]=(BYTE)((VH[i]>>24)&0xFF);\r
+ output[i*4+2]=(BYTE)((VH[i]>>16)&0xFF);\r
+ output[i*4+1]=(BYTE)((VH[i]>>8)&0xFF);\r
+ output[i*4+0]=(BYTE)(VH[i]&0xFF);\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+///*****************************************\r
+// Copyright (C)2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <sha1.h>\r
+// @author Jau-chih.Tseng@ite.com.tw\r
+// @date 2010/06/04\r
+// @fileversion: COMMON_FILE_1.01\r
+//******************************************/\r
+\r
+#ifndef _SHA_1_H_\r
+#define _SHA_1_H_\r
+\r
+#ifdef _MCU_8051_\r
+ #include "Mcu.h"\r
+#endif\r
+\r
+#include <string.h>\r
+\r
+#if Debug_message\r
+ #include <stdio.h>\r
+#endif\r
+\r
+#include "config.h"\r
+#include "typedef.h"\r
+\r
+#ifndef HDCP_DEBUG_PRINTF\r
+ #define HDCP_DEBUG_PRINTF(x)\r
+#endif //HDCP_DEBUG_PRINTF\r
+\r
+#ifndef HDCP_DEBUG_PRINTF1\r
+ #define HDCP_DEBUG_PRINTF1(x)\r
+#endif //HDCP_DEBUG_PRINTF1\r
+\r
+#ifndef HDCP_DEBUG_PRINTF2\r
+ #define HDCP_DEBUG_PRINTF2(x)\r
+#endif //HDCP_DEBUG_PRINTF2\r
+\r
+\r
+#ifndef DISABLE_HDCP\r
+void SHA_Simple(void *p,WORD len,BYTE *output);\r
+void SHATransform(ULONG * h);\r
+#endif\r
+\r
+#endif // _SHA_1_H_\r
--- /dev/null
+///*****************************************\r
+// Copyright (C) 2009-2014\r
+// ITE Tech. Inc. All Rights Reserved\r
+// Proprietary and Confidential\r
+///*****************************************\r
+// @file <typedef.h>\r
+// @author Jau-Chih.Tseng@ite.com.tw\r
+// @date 2012/12/20\r
+// @fileversion: ITE_HDMITX_SAMPLE_3.14\r
+//******************************************/\r
+\r
+#ifndef _TYPEDEF_H_\r
+#define _TYPEDEF_H_\r
+\r
+//////////////////////////////////////////////////\r
+// data type\r
+//////////////////////////////////////////////////\r
+#ifdef _MCU_8051_\r
+ #define _CODE code\r
+ #define _DATA data\r
+ #define _XDATA xdata\r
+ #define _IDATA idata\r
+ typedef bit BOOL ;\r
+#else\r
+ #define _CODE const\r
+ #define _DATA\r
+ #define _IDATA\r
+ #define _XDATA\r
+ typedef int BOOL ;\r
+#endif // _MCU_8051_\r
+\r
+typedef _CODE unsigned char cBYTE;\r
+\r
+\r
+typedef char CHAR,*PCHAR ;\r
+typedef unsigned char uchar,*puchar ;\r
+typedef unsigned char UCHAR,*PUCHAR ;\r
+typedef unsigned char byte,*pbyte ;\r
+typedef unsigned char BYTE,*PBYTE ;\r
+\r
+typedef short SHORT,*PSHORT ;\r
+typedef unsigned short *pushort ;\r
+typedef unsigned short USHORT,*PUSHORT ;\r
+typedef unsigned short word,*pword ;\r
+typedef unsigned short WORD,*PWORD ;\r
+typedef unsigned int UINT,*PUINT ;\r
+\r
+typedef long LONG,*PLONG ;\r
+typedef unsigned long *pulong ;\r
+typedef unsigned long ULONG,*PULONG ;\r
+typedef unsigned long dword,*pdword ;\r
+typedef unsigned long DWORD,*PDWORD ;\r
+\r
+#define FALSE 0\r
+#define TRUE 1\r
+\r
+#define SUCCESS 0\r
+#define FAIL -1\r
+\r
+#define ON 1\r
+#define OFF 0\r
+\r
+#define LO_ACTIVE TRUE\r
+#define HI_ACTIVE FALSE\r
+\r
+\r
+typedef enum _SYS_STATUS {\r
+ ER_SUCCESS = 0,\r
+ ER_FAIL,\r
+ ER_RESERVED\r
+} SYS_STATUS ;\r
+\r
+#define ABS(x) (((x)>=0)?(x):(-(x)))\r
+\r
+\r
+\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////\r
+// Video Data Type\r
+///////////////////////////////////////////////////////////////////////\r
+\r
+#define F_MODE_RGB444 0\r
+#define F_MODE_YUV422 1\r
+#define F_MODE_YUV444 2\r
+#define F_MODE_CLRMOD_MASK 3\r
+\r
+\r
+#define F_MODE_INTERLACE 1\r
+\r
+#define F_VIDMODE_ITU709 (1<<4)\r
+#define F_VIDMODE_ITU601 0\r
+\r
+#define F_VIDMODE_0_255 0\r
+#define F_VIDMODE_16_235 (1<<5)\r
+\r
+#define F_VIDMODE_EN_UDFILT (1<<6)\r
+#define F_VIDMODE_EN_DITHER (1<<7)\r
+\r
+#define T_MODE_CCIR656 (1<<0)\r
+#define T_MODE_SYNCEMB (1<<1)\r
+#define T_MODE_INDDR (1<<2)\r
+#define T_MODE_PCLKDIV2 (1<<3)\r
+#define T_MODE_DEGEN (1<<4)\r
+#define T_MODE_SYNCGEN (1<<5)\r
+/////////////////////////////////////////////////////////////////////\r
+// Packet and Info Frame definition and datastructure.\r
+/////////////////////////////////////////////////////////////////////\r
+\r
+\r
+#define VENDORSPEC_INFOFRAME_TYPE 0x81\r
+#define AVI_INFOFRAME_TYPE 0x82\r
+#define SPD_INFOFRAME_TYPE 0x83\r
+#define AUDIO_INFOFRAME_TYPE 0x84\r
+#define MPEG_INFOFRAME_TYPE 0x85\r
+\r
+#define VENDORSPEC_INFOFRAME_VER 0x01\r
+#define AVI_INFOFRAME_VER 0x02\r
+#define SPD_INFOFRAME_VER 0x01\r
+#define AUDIO_INFOFRAME_VER 0x01\r
+#define MPEG_INFOFRAME_VER 0x01\r
+\r
+#define VENDORSPEC_INFOFRAME_LEN 5\r
+#define AVI_INFOFRAME_LEN 13\r
+#define SPD_INFOFRAME_LEN 25\r
+#define AUDIO_INFOFRAME_LEN 10\r
+#define MPEG_INFOFRAME_LEN 10\r
+\r
+#define ACP_PKT_LEN 9\r
+#define ISRC1_PKT_LEN 16\r
+#define ISRC2_PKT_LEN 16\r
+\r
+typedef union _VendorSpecific_InfoFrame\r
+{\r
+ struct {\r
+ BYTE Type ;\r
+ BYTE Ver ;\r
+ BYTE Len ;\r
+\r
+ BYTE CheckSum;\r
+\r
+ BYTE IEEE_0;//PB1\r
+ BYTE IEEE_1;//PB2\r
+ BYTE IEEE_2;//PB3\r
+\r
+ BYTE Rsvd:5 ;//PB4\r
+ BYTE HDMI_Video_Format:3 ;\r
+\r
+ BYTE Reserved_PB5:4 ;//PB5\r
+ BYTE _3D_Structure:4 ;\r
+\r
+ BYTE Reserved_PB6:4 ;//PB6\r
+ BYTE _3D_Ext_Data:4 ;\r
+ } info ;\r
+ struct {\r
+ BYTE VS_HB[3] ;\r
+ BYTE CheckSum;\r
+ BYTE VS_DB[28] ;\r
+ } pktbyte ;\r
+} VendorSpecific_InfoFrame ;\r
+\r
+typedef union _AVI_InfoFrame\r
+{\r
+\r
+ struct {\r
+ BYTE Type;\r
+ BYTE Ver;\r
+ BYTE Len;\r
+\r
+ BYTE checksum ;\r
+\r
+ BYTE Scan:2;\r
+ BYTE BarInfo:2;\r
+ BYTE ActiveFmtInfoPresent:1;\r
+ BYTE ColorMode:2;\r
+ BYTE FU1:1;\r
+\r
+ BYTE ActiveFormatAspectRatio:4;\r
+ BYTE PictureAspectRatio:2;\r
+ BYTE Colorimetry:2;\r
+\r
+ BYTE Scaling:2;\r
+ BYTE FU2:6;\r
+\r
+ BYTE VIC:7;\r
+ BYTE FU3:1;\r
+\r
+ BYTE PixelRepetition:4;\r
+ BYTE FU4:4;\r
+\r
+ short Ln_End_Top;\r
+ short Ln_Start_Bottom;\r
+ short Pix_End_Left;\r
+ short Pix_Start_Right;\r
+ } info;\r
+\r
+ struct {\r
+ BYTE AVI_HB[3];\r
+ BYTE checksum ;\r
+ BYTE AVI_DB[AVI_INFOFRAME_LEN];\r
+ } pktbyte;\r
+} AVI_InfoFrame;\r
+\r
+typedef union _Audio_InfoFrame {\r
+\r
+ struct {\r
+ BYTE Type;\r
+ BYTE Ver;\r
+ BYTE Len;\r
+ BYTE checksum ;\r
+\r
+ BYTE AudioChannelCount:3;\r
+ BYTE RSVD1:1;\r
+ BYTE AudioCodingType:4;\r
+\r
+ BYTE SampleSize:2;\r
+ BYTE SampleFreq:3;\r
+ BYTE Rsvd2:3;\r
+\r
+ BYTE FmtCoding;\r
+\r
+ BYTE SpeakerPlacement;\r
+\r
+ BYTE Rsvd3:3;\r
+ BYTE LevelShiftValue:4;\r
+ BYTE DM_INH:1;\r
+ } info;\r
+\r
+ struct {\r
+ BYTE AUD_HB[3];\r
+ BYTE checksum ;\r
+ BYTE AUD_DB[5];\r
+ } pktbyte;\r
+\r
+} Audio_InfoFrame;\r
+\r
+typedef union _MPEG_InfoFrame {\r
+ struct {\r
+ BYTE Type;\r
+ BYTE Ver;\r
+ BYTE Len;\r
+ BYTE checksum ;\r
+\r
+ ULONG MpegBitRate;\r
+\r
+ BYTE MpegFrame:2;\r
+ BYTE Rvsd1:2;\r
+ BYTE FieldRepeat:1;\r
+ BYTE Rvsd2:3;\r
+ } info;\r
+ struct {\r
+ BYTE MPG_HB[3];\r
+ BYTE checksum ;\r
+ BYTE MPG_DB[MPEG_INFOFRAME_LEN];\r
+ } pktbyte;\r
+} MPEG_InfoFrame;\r
+\r
+typedef union _SPD_InfoFrame {\r
+ struct {\r
+ BYTE Type;\r
+ BYTE Ver;\r
+ BYTE Len;\r
+ BYTE checksum ;\r
+\r
+ char VN[8];\r
+ char PD[16];\r
+ BYTE SourceDeviceInfomation;\r
+ } info;\r
+ struct {\r
+ BYTE SPD_HB[3];\r
+ BYTE checksum ;\r
+ BYTE SPD_DB[SPD_INFOFRAME_LEN];\r
+ } pktbyte;\r
+} SPD_InfoFrame;\r
+\r
+///////////////////////////////////////////////////////////////////////////\r
+// Using for interface.\r
+///////////////////////////////////////////////////////////////////////////\r
+\r
+#define PROG 1\r
+#define INTERLACE 0\r
+#define Vneg 0\r
+#define Hneg 0\r
+#define Vpos 1\r
+#define Hpos 1\r
+\r
+typedef struct {\r
+ WORD H_ActiveStart;\r
+ WORD H_ActiveEnd;\r
+ WORD H_SyncStart;\r
+ WORD H_SyncEnd;\r
+ WORD V_ActiveStart;\r
+ WORD V_ActiveEnd;\r
+ WORD V_SyncStart;\r
+ WORD V_SyncEnd;\r
+ WORD V2_ActiveStart;\r
+ WORD V2_ActiveEnd;\r
+ WORD HTotal;\r
+ WORD VTotal;\r
+} CEAVTiming;\r
+\r
+typedef struct {\r
+ BYTE VIC ;\r
+ BYTE PixelRep ;\r
+ WORD HActive;\r
+ WORD VActive;\r
+ WORD HTotal;\r
+ WORD VTotal;\r
+ ULONG PCLK;\r
+ BYTE xCnt;\r
+ WORD HFrontPorch;\r
+ WORD HSyncWidth;\r
+ WORD HBackPorch;\r
+ BYTE VFrontPorch;\r
+ BYTE VSyncWidth;\r
+ BYTE VBackPorch;\r
+ BYTE ScanMode:1;\r
+ BYTE VPolarity:1;\r
+ BYTE HPolarity:1;\r
+} HDMI_VTiming;\r
+\r
+//////////////////////////////////////////////////////////////////\r
+// Audio relate definition and macro.\r
+//////////////////////////////////////////////////////////////////\r
+\r
+// 2008/08/15 added by jj_tseng@chipadvanced\r
+#define F_AUDIO_ON (1<<7)\r
+#define F_AUDIO_HBR (1<<6)\r
+#define F_AUDIO_DSD (1<<5)\r
+#define F_AUDIO_NLPCM (1<<4)\r
+#define F_AUDIO_LAYOUT_1 (1<<3)\r
+#define F_AUDIO_LAYOUT_0 (0<<3)\r
+\r
+// HBR - 1100\r
+// DSD - 1010\r
+// NLPCM - 1001\r
+// LPCM - 1000\r
+\r
+#define T_AUDIO_MASK 0xF0\r
+#define T_AUDIO_OFF 0\r
+#define T_AUDIO_HBR (F_AUDIO_ON|F_AUDIO_HBR)\r
+#define T_AUDIO_DSD (F_AUDIO_ON|F_AUDIO_DSD)\r
+#define T_AUDIO_NLPCM (F_AUDIO_ON|F_AUDIO_NLPCM)\r
+#define T_AUDIO_LPCM (F_AUDIO_ON)\r
+\r
+// for sample clock\r
+#define AUDFS_22p05KHz 4\r
+#define AUDFS_44p1KHz 0\r
+#define AUDFS_88p2KHz 8\r
+#define AUDFS_176p4KHz 12\r
+\r
+#define AUDFS_24KHz 6\r
+#define AUDFS_48KHz 2\r
+#define AUDFS_96KHz 10\r
+#define AUDFS_192KHz 14\r
+\r
+#define AUDFS_768KHz 9\r
+\r
+#define AUDFS_32KHz 3\r
+#define AUDFS_OTHER 1\r
+\r
+// Audio Enable\r
+#define ENABLE_SPDIF (1<<4)\r
+#define ENABLE_I2S_SRC3 (1<<3)\r
+#define ENABLE_I2S_SRC2 (1<<2)\r
+#define ENABLE_I2S_SRC1 (1<<1)\r
+#define ENABLE_I2S_SRC0 (1<<0)\r
+\r
+#define AUD_SWL_NOINDICATE 0x0\r
+#define AUD_SWL_16 0x2\r
+#define AUD_SWL_17 0xC\r
+#define AUD_SWL_18 0x4\r
+#define AUD_SWL_20 0xA // for maximum 20 bit\r
+#define AUD_SWL_21 0xD\r
+#define AUD_SWL_22 0x5\r
+#define AUD_SWL_23 0x9\r
+#define AUD_SWL_24 0xB\r
+\r
+\r
+#endif // _TYPEDEF_H_\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff