regulator: qcom_spmi: Update mvs1/mvs2 switches on pm8941

commit 93bfe79b03365f410aa91caf04263173c008ecdf upstream.

The mvs1 and mvs2 switches are actually called 5vs1 and 5vs2 on
some datasheets. Let's rename them to match the datasheets and
also match the RPM based regulator driver which calls these by
their 5vs names (see qcom_smd-regulator.c). There aren't any
users of these regulators so far, so there aren't any concerns of
DT ABI breakage here. While we're here making updates to the
switches, also mandate usage of the OCP irq for these switches
too.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: e92a4047419c ("regulator: Add QCOM SPMI regulator driver")
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
index b743c18d7885f09ee23c282e670b1c402c752636..e0381c28773de5ab972a8368012760cbf8ca1b29 100644 (file)
--- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
@@ -83,7 +83,7 @@ pm8916:
 pm8941:
        s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
        l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3,
-       mvs1, mvs2
+       5vs1, 5vs2
 
 The content of each sub-node is defined by the standard binding for regulators -
 see regulator.txt - with additional custom properties described below:

diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c
index 45cc2d39682c7f33693b77dcda7e808becfeb9f0..fee6457e3111f9fb4e0ede3c670aba43902fa6d9 100644 (file)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -1470,8 +1470,8 @@ static const struct spmi_regulator_data pm8941_regulators[] = {
        { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
        { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
        { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
-       { "mvs1", 0x8300, "vin_5vs", },
-       { "mvs2", 0x8400, "vin_5vs", },
+       { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
+       { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
        { }
 };