Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 212958025bde2ceeac457db6835436c7060bdab8..0f782c9a8fde14824a9db8b481fa41b020cd9850 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1102,7 +1102,8 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
 }
 
 // Load, store, and memory fence
-def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
+def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
+             TB, Requires<[HasSSE1]>;
 
 // MXCSR register
 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),

diff --git a/test/MC/AsmParser/X86/x86_32-new-encoder.s b/test/MC/AsmParser/X86/x86_32-new-encoder.s
index bc716da829815b335656e75afd532051da56cc47..2400f5ad0125da35a6ceba66a113d3d5e9731bf9 100644 (file)
--- a/test/MC/AsmParser/X86/x86_32-new-encoder.s
+++ b/test/MC/AsmParser/X86/x86_32-new-encoder.s
@@ -1,5 +1,8 @@
 // RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
 
+       sfence
+// CHECK: sfence
+// CHECK: encoding: [0x0f,0xae,0xf8]
        lfence
 // CHECK: lfence
 // CHECK: encoding: [0x0f,0xae,0xe8]