ARM: S3C64XX: Gate some more clocks by default

Gate the AC'97 and CF clocks by default. The drivers will enable them
required.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4aeba8ace23ad4a8bdb80df742657085..b58274f80cf9e8137e527c5bda3b0a2c5ffb95a8 100644 (file)
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -201,6 +201,15 @@ static struct clk init_clocks_off[] = {
                .parent         = &clk_48m,
                .enable         = s3c64xx_sclk_ctrl,
                .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
+       }, {
+               .name           = "ac97",
+               .parent         = &clk_p,
+               .ctrlbit        = S3C_CLKCON_PCLK_AC97,
+       }, {
+               .name           = "cfcon",
+               .parent         = &clk_h,
+               .enable         = s3c64xx_hclk_ctrl,
+               .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
        }, {
                .name           = "dma0",
                .parent         = &clk_h,
@@ -284,16 +293,7 @@ static struct clk init_clocks[] = {
                .name           = "watchdog",
                .parent         = &clk_p,
                .ctrlbit        = S3C_CLKCON_PCLK_WDT,
-       }, {
-               .name           = "ac97",
-               .parent         = &clk_p,
-               .ctrlbit        = S3C_CLKCON_PCLK_AC97,
-       }, {
-               .name           = "cfcon",
-               .parent         = &clk_h,
-               .enable         = s3c64xx_hclk_ctrl,
-               .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
-       }
+       },
 };
 
 static struct clk clk_hsmmc0 = {