return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
}
- return SDValue();
+ return Op;
}
//! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
}
- return SDValue();
+ return Op;
}
//! Lower ISD::SETCC
// These are really Legal; caller falls through into that case.
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
- return SDValue();
+ return Op;
if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
Subtarget->is64Bit())
- return SDValue();
+ return Op;
DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
if (SrcVT == MVT::i64) {
// We only handle SSE2 f64 target here; caller can handle the rest.
if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
- return SDValue();
+ return Op;
return LowerUINT_TO_FP_i64(Op, DAG);
} else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
SDValue FIST = Vals.first, StackSlot = Vals.second;
- if (FIST.getNode() == 0) return SDValue();
+ if (FIST.getNode() == 0) return Op;
// Load the result.
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),